ST72F324J6T6 STMicroelectronics, ST72F324J6T6 Datasheet - Page 97

• Manufacturer Part Number: ST72F324J6T6
• Description: IC MCU 8BIT 32K 44-TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324J6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: ST7
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• No. Of Pwm Channels: 1
• Rohs Compliant: Yes
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1024 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 3.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7F521-IND/USB, ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 1KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3.8V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: TQFP
• For Use With: 497-8222 - UPS (LINE INTERACTIVE - 450W)497-8436 - BOARD EVAL UPS 450W VOUT=220V497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: In Transition
• Other names: 497-2108

ST72324Bxx
10.4.3
General description
Figure 50
registers:
The SPI is connected to external devices through four pins:
Figure 50. Serial peripheral interface block diagram
Functional description
A basic example of interconnections between a single master and a single slave is
illustrated in
The MOSI pins are connected together and the MISO pins are connected together. In this
way data is transferred serially between master and slave (most significant bit first).
MOSI
MISO
SCK
SS
–
–
–
–
–
–
–
SPI Control Register (SPICR)
SPI Control/Status Register (SPICSR)
SPI Data Register (SPIDR)
MISO: Master In / Slave Out data
MOSI: Master Out / Slave In data
SCK: Serial Clock out by SPI masters and input by SPI slaves
SS: Slave select: This input signal acts as a ‘chip select’ to let the SPI master
communicate with slaves individually and to avoid contention on the data lines.
Slave SS inputs can be driven by standard I/O ports on the master MCU.
shows the serial peripheral interface (SPI) block diagram. The SPI has three
SOD
Figure
bit
SPIDR
51.
8-bit Shift Register
Read Buffer
Serial clock
generator
Master
control
Data/Address bus
Read
Write
7
SPIF WCOL
SPIE SPE
7
SPR2
OVR
control
state
SPI
Interrupt
request
MODF
MSTR
On-chip peripherals
CPOL
0
CPHA
SOD
SS
SPICR
SPICSR
SSM
SPR1
1
0
SPR0
SSI
97/193
0
0