ST72F561J6T6 STMicroelectronics, ST72F561J6T6 Datasheet - Page 170
![MCU 8BIT 32KB FLASH 44-LQFP](/photos/6/84/68458/497-44-tqfp_44-lqfp_sml.jpg)
ST72F561J6T6
Manufacturer Part Number
ST72F561J6T6
Description
MCU 8BIT 32KB FLASH 44-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F561K6T6.pdf
(265 pages)
Specifications of ST72F561J6T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LINSCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-LQFP
Processor Series
ST72F5x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
497-8374 - BOARD DEVELOPMENT FOR ST72F561497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5617
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F561J6T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
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ST72561
10.9 beCAN CONTROLLER (beCAN)
The beCAN controller (Basic Enhanced CAN), in-
terfaces the CAN network and supports the CAN
protocol version 2.0A and B. It has been designed
to manage high number of incoming messages ef-
ficiently with a minimum CPU load. It also meets
the priority requirements for transmit messages.
10.9.1 Main Features
■
■
Transmission
■
■
Reception
■
■
■
■
Management
■
■
Figure 94. CAN Network Topology
170/265
Supports CAN protocol version 2.0 A, B Active
Bit rates up to 1Mbit/s
2 transmit mailboxes
Configurable transmit priority
1 receive FIFO with three stages
6 scalable filter banks
Identifier list feature
Configurable FIFO overrun
Maskable interrupts
Software-efficient mailbox mapping at a unique
address space
CAN Bus
CAN
Rx
CAN
High
Application
ST9 MCU
CAN
Transceiver
CAN
Controller
CAN
CAN
Tx
Low
10.9.2 General Description
In today’s CAN applications, the number of nodes
in a network is increasing and often several net-
works are linked together via gateways. Typically
the number of messages in the system (and thus
to be handled by each node) has significantly in-
creased. In addition to the application messages,
Network Management and Diagnostic messages
have been introduced.
– An enhanced filtering mechanism is required to
Furthermore, application tasks require more CPU
time, therefore real-time constraints caused by
message reception have to be reduced.
– A receive FIFO scheme allows the CPU to be
The standard HLP (Higher Layer Protocol) based
on standard CAN drivers requires an efficient in-
terface to the CAN controller.
– All mailboxes and registers are organized in 16-
handle each type of message.
dedicated to application tasks for a long time pe-
riod without losing messages.
byte pages mapped at the same address and se-
lected via a page select register.
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