ST72F561J6T6 STMicroelectronics, ST72F561J6T6 Datasheet - Page 35
![MCU 8BIT 32KB FLASH 44-LQFP](/photos/6/84/68458/497-44-tqfp_44-lqfp_sml.jpg)
ST72F561J6T6
Manufacturer Part Number
ST72F561J6T6
Description
MCU 8BIT 32KB FLASH 44-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F561K6T6.pdf
(265 pages)
Specifications of ST72F561J6T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LINSCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-LQFP
Processor Series
ST72F5x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
497-8374 - BOARD DEVELOPMENT FOR ST72F561497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5617
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F561J6T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
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INTERRUPTS (Cont’d)
7.6 EXTERNAL INTERRUPTS
7.6.1 I/O Port Interrupt Sensitivity
The external interrupt sensitivity is controlled by
the ISxx bits in the EICR register
control allows up to four fully independent external
interrupt source sensitivities.
Each external interrupt source can be generated
on four (or five) different events on the pin:
■
■
Figure 21. External Interrupt Control Bits
Falling edge
Rising edge
PA0
PC1
PD0
PB0
PORT A [7:0] INTERRUPTS
PORT C [2:1] INTERRUPTS
PORT D [7:6, 4, 1:0] INTERRUPTS
PORT B [5:0] INTERRUPTS
PADDR.0
PCDDR.7
PDDDR.0
PBDDR.0
PAOR.0
PCOR.7
PDOR.0
PBOR.0
(Figure
SENSITIVITY
SENSITIVITY
IS00
IS20
SENSITIVITY
SENSITIVITY
IS30
IS10
CONTROL
CONTROL
21). This
CONTROL
CONTROL
EICR
EICR
EICR
EICR
IS01
IS21
IS31
IS11
Oscillator
■
■
To guarantee correct functionality, the sensitivity
bits in the EICR register can be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3). This means that interrupts must
be disabled before changing sensitivity.
The pending interrupts are cleared by writing a dif-
ferent value in the ISx[1:0] of the EICR.
AWUFH
PA0
PA1
PA2
PA3
PC1
PC2
PD0
PD1
PD4
PD6
PD7
PB0
PB1
PB2
PB3
PB4
PB5
Falling and rising edge
Falling edge and low level
PA4
PA5
PA6
PA7
To Timer Input Capture 1
/ AWUPR
ei2 INTERRUPT SOURCE
ei0 INTERRUPT SOURCE
ei3 INTERRUPT SOURCE
ei1 INTERRUPT SOURCE
ST72561
35/265
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