ST72F561J6T6 STMicroelectronics, ST72F561J6T6 Datasheet - Page 63
![MCU 8BIT 32KB FLASH 44-LQFP](/photos/6/84/68458/497-44-tqfp_44-lqfp_sml.jpg)
ST72F561J6T6
Manufacturer Part Number
ST72F561J6T6
Description
MCU 8BIT 32KB FLASH 44-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F561K6T6.pdf
(265 pages)
Specifications of ST72F561J6T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LINSCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-LQFP
Processor Series
ST72F5x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
497-8374 - BOARD DEVELOPMENT FOR ST72F561497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5617
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F561J6T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
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PWM AUTO-RELOAD TIMER (Cont’d)
10.3.2 Functional Description
Counter
The free running 8-bit counter is fed by the output
of the prescaler, and is incremented on every ris-
ing edge of the clock signal.
It is possible to read or write the contents of the
counter on the fly by reading or writing the Counter
Access register (ARTCAR).
When a counter overflow occurs, the counter is
automatically reloaded with the contents of the
ARTARR register (the prescaler is not affected).
Counter clock and prescaler
The counter clock frequency is given by:
f
The timer counter’s input clock (f
7-bit programmable prescaler, which selects one
of the eight available taps of the prescaler, as de-
fined by CC[2:0] bits in the Control/Status Register
(ARTCSR). Thus the division factor of the prescal-
er can be set to 2
This f
the EXCL bit of the ARTCSR register and can be
either the f
The clock input to the counter is enabled by the
TCE (Timer Counter Enable) bit in the ARTCSR
register. When TCE is reset, the counter is
stopped and the prescaler and counter contents
are frozen. When TCE is set, the counter runs at
the rate of the selected clock source.
Figure 41. Output Compare Control
COUNTER
INPUT
COUNTER
f
COUNTER
PWMx
PWMDCRx
OCRx
= f
CPU
frequency source is selected through
INPUT
or an external input frequency f
n
/ 2
FDh
(where n = 0, 1,..7).
CC[2:0]
FEh
FDh
INPUT
ARTARR=FDh
FFh
) feeds the
FDh
EXT
FDh
.
Counter and Prescaler Initialization
After RESET, the counter and the prescaler are
cleared and f
The counter can be initialized by:
– Writing to the ARTARR register and then setting
– Writing to the ARTCAR counter access register,
In both cases the 7-bit prescaler is also cleared,
whereupon counting will start from a known value.
Direct access to the prescaler is not possible.
Output compare control
The timer compare function is based on four differ-
ent comparisons with the counter (one for each
PWMx output). Each comparison is made be-
tween the counter value and an output compare
register (OCRx) value. This OCRx register can not
be accessed directly, it is loaded from the duty cy-
cle register (PWMDCRx) at each overflow of the
counter.
This double buffering method avoids glitch gener-
ation when changing the duty cycle on the fly.
FEh
the FCRL (Force Counter Re-Load) and the TCE
(Timer Counter Enable) bits in the ARTCSR reg-
ister.
FFh
INPUT
FEh
FDh
= f
CPU
FEh
.
FEh
FFh
ST72561
63/265
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