ST10R172LT1 STMicroelectronics, ST10R172LT1 Datasheet - Page 58

• Manufacturer Part Number: ST10R172LT1
• Description: MCU 16BIT ROMLESS LV 100TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10R172LT1

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-TQFP, 100-VQFP
• Controller Family/series: ST10
• No. Of I/o's: 77
• Ram Memory Size: 1KB
• Cpu Speed: 50MHz
• No. Of Timers: 5
• Embedded Interface Type: SPI, USART
• No. Of Pwm Channels: 1
• Rohs Compliant: Yes
• Processor Series: ST10R1x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SSP, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: In Transition

ST10R172L - ELECTRICAL CHARACTERISTICS
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1
Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
The leading edge of the respective command depends on RW-delay.
READY (or READY) sampled HIGH (resp. LOW) at this sampling point generates a
READY controlled waitstate, READY (resp. READY) sampled LOW (resp. HIGH) at this
sampling point terminates the currently running bus cycle.
READY (resp. READY) may be deactivated in response to the trailing (rising) edge of the
corresponding command (RD or WR).
If the Asynchronous READY (or READY) signal does not fulfill the indicated setup and
hold times with respect to CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill t
37 in order to be safely synchronized. This is guaranteed, if READY is removed in
response to the command (see Note 4)).
Command
READY
READY
READY
READY
CLKOUT
RD, WR
Async
Async
Sync
Sync
ALE
t
t
t
58
58
32
Figure 21 CLKOUT and READY/READY
3)
3)
t
t
t
Running cycle 1)
t
59
59
34
30
2)
5)
t
t
33
31
t
t
t
t
35
58
35
58
5)
3)
3)
t
t
3)
37
37
3)
t
t
t
t
36
59
36
59
t
29
t
t
35
35
READY
3)
waitstate
3)
t
t
36
36
MUX/Tristate 6)
t
t
60
60
4)
4)
see 6)
7)