STR912FAW47X6 STMicroelectronics, STR912FAW47X6 Datasheet - Page 26
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STR912FAW47X6
Manufacturer Part Number
STR912FAW47X6
Description
MCU ARM9 2048KB FLASH 128LQFP
Manufacturer
STMicroelectronics
Series
STR9r
Datasheet
1.STEVAL-IFW001V1.pdf
(102 pages)
Specifications of STR912FAW47X6
Core Processor
ARM9
Core Size
32-Bit
Speed
96MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
2MB (2M x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 2 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
Processor Series
STR912x
Core
ARM966E-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
96 KB
Interface Type
CAN, I2C, IrDA, SSP, UART, USB
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
80
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MCBSTR9, MCBSTR9U, MCBSTR9UME, KSDK-STR912-PLUS, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
STR9
Device Core
ARM966E-S
Device Core Size
16/32Bit
Frequency (max)
96MHz
Total Internal Ram Size
96KB
# I/os (max)
80
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2/3.6V
Operating Supply Voltage (min)
1.65/1.77/2.5/2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
128
Package Type
LQFP
For Use With
MCBSTR9UME - BOARD EVAL MCBSTR9 + ULINK-MEMCBSTR9U - BOARD EVAL MCBSTR9 + ULINK2MCBSTR9 - BOARD EVAL STM STR9 SERIES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-9039
STR912FAW47X6
STR912FAW47X6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STR912FAW47X6
Manufacturer:
ST
Quantity:
1 560
Company:
Part Number:
STR912FAW47X6
Manufacturer:
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Quantity:
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Functional overview
3.13.2
3.13.3
3.13.4
3.13.5
3.13.6
26/102
Supply voltage dropout
LVD circuitry will always cause a global reset if the CPU’s V
threshold of 1.4 V.
However, the LVD trigger threshold to cause a global reset for the I/O ring’s V
set to one of two different levels, depending if V
3.3 V, or 3.0V to 3.6 V. If V
threshold is 2.4 V. If V
choice of trigger level is made by STR91xFA device configuration software from
STMicroelectronics or IDE from 3rd parties, and is programmed into the STR91xFA device
along with other configurable items through the JTAG interface when the Flash memory is
programmed.
CPU firmware may prevent some LVD resets if desired by writing a control register at run-
time. Firmware may also disable the LVD completely for lowest-power operation when an
external LVD device is being used.
Watchdog timer
The STR91xFA has a 16-bit down-counter (not one of the four TIM timers) that can be used
as a watchdog timer or as a general purpose free-running timer/counter. The clock source is
the peripheral clock from the APB, and an 8-bit clock pre-scaler is available. When enabled
by firmware as a watchdog, this timer will cause a system reset if firmware fails to
periodically reload this timer before the terminal count of 0x0000 occurs, ensuring firmware
sanity. The watchdog function is off by default after a reset and must be enabled by
firmware.
External RESET_INn pin
This input signal is active-low with hystereses (V
reset signals on the circuit board (such as closure to ground from a push-button) may be
connected directly to the RESET_INn pin, but an external pull-up resistor to V
present as there is no internal pullup on the RESET_INn pin.
A valid active-low input signal of t
reset within the STR91xFA. There is also a RESET_OUTn pin on the STR91xFA that can
drive other system components on the circuit board. RESET_OUTn is active-low and has
the same timing of the Power-On-Reset (POR) shown next, t
Power-up
The LVD circuitry will always generate a global reset when the STR91xFA powers up,
meaning internal reset is active until V
POR condition has a duration of t
address 0x0000.0000 in Flash memory. It is not possible for the CPU to boot from any other
source other than Flash memory.
JTAG debug command
When the STR91xFA is in JTAG debug mode, an external device which controls the JTAG
interface can command a system reset to the STR91xFA over the JTAG channel.
DDQ
DDQ
operation is 3.0 V and 3.6 V, the LVD threshold is 2.7 V. The
Doc ID 13495 Rev 6
operation is at 2.7 V to 3.3 V, the LVD dropout trigger
RINMIN
POR
, after which the CPU will fetch its first instruction from
DDQ
duration on the RESET_INn pin will cause a system
and V
DDQ
DD
HYS
are both above the LVD thresholds. This
will be operated in the range of 2.7 V to
). Other open-drain, active-low system
DD
POR
source drops below it’s fixed
.
STR91xFAxxx
DDQ
DDQ
source is
must be