STR912FAW47X6 STMicroelectronics, STR912FAW47X6 Datasheet - Page 31
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STR912FAW47X6
Manufacturer Part Number
STR912FAW47X6
Description
MCU ARM9 2048KB FLASH 128LQFP
Manufacturer
STMicroelectronics
Series
STR9r
Datasheet
1.STEVAL-IFW001V1.pdf
(102 pages)
Specifications of STR912FAW47X6
Core Processor
ARM9
Core Size
32-Bit
Speed
96MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
2MB (2M x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 2 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
Processor Series
STR912x
Core
ARM966E-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
96 KB
Interface Type
CAN, I2C, IrDA, SSP, UART, USB
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
80
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MCBSTR9, MCBSTR9U, MCBSTR9UME, KSDK-STR912-PLUS, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
STR9
Device Core
ARM966E-S
Device Core Size
16/32Bit
Frequency (max)
96MHz
Total Internal Ram Size
96KB
# I/os (max)
80
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2/3.6V
Operating Supply Voltage (min)
1.65/1.77/2.5/2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
128
Package Type
LQFP
For Use With
MCBSTR9UME - BOARD EVAL MCBSTR9 + ULINK-MEMCBSTR9U - BOARD EVAL MCBSTR9 + ULINK2MCBSTR9 - BOARD EVAL STM STR9 SERIES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-9039
STR912FAW47X6
STR912FAW47X6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STR912FAW47X6
Manufacturer:
ST
Quantity:
1 560
Company:
Part Number:
STR912FAW47X6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Company:
Part Number:
STR912FAW47X6T
Manufacturer:
STMicroelectronics
Quantity:
10 000
STR91xFAxxx
3.18
The STR91xFA MAC includes the following features:
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A 32-bit burst DMA channel residing on the AHB is dedicated to the Ethernet MAC for high-
speed data transfers, side-stepping the CPU for minimal CPU impact during transfers. This
DMA channel includes the following features:
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USB 2.0 slave device interface with DMA
The STR91xFA provides a USB slave controller that implements both the OSI Physical and
Data Link layers for direct bus connection by an external USB host on pins USBDP and
USBPN. The USB interface detects token packets, handles data transmission and
reception, and processes handshake packets as required by the USB 2.0 standard.
The USB slave interface includes the following features:
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Supports 10 and 100 Mbps rates
Tagged MAC frame support (VLAN support)
Half duplex (CSMA/CD) and full duplex operation
MAC control sublayer (control frames) support
32-bit CRC generation and removal
Several address filtering modes for physical and multicast address (multicast and group
addresses)
32-bit status code for each transmitted or received frame
Internal FIFOs to buffer transmit and receive frames. Transmit FIFO depth is 4 words
(32 bits each), and the receive FIFO is 16 words deep.
Direct SRAM to MAC transfers of transmit frames with the related status, by descriptor
chain
Direct MAC to SRAM transfers of receive frames with the related status, by descriptor
chain
Open and Closed descriptor chain management
Supports USB low and full-speed transfers (12 Mbps), certified to comply with the USB
2.0 specification
Supports isochronous, bulk, control, and interrupt endpoints
Configurable number of endpoints allowing a mixture of up to 20 single-buffered
monodirectional endpoints or up to 10 double-buffered bidirectional endpoints
Dedicated, dual-port 2 Kbyte USB Packet Buffer SRAM. One port of the SRAM is
connected by a Packet Buffer Interface (PBI) on the USB side, and the CPU connects
to the other SRAM port.
CRC generation and checking
NRZI encoding-decoding and bit stuffing
USB suspend resume operations
Doc ID 13495 Rev 6
Functional overview
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