ST10F273M-4T3 STMicroelectronics, ST10F273M-4T3 Datasheet - Page 143

• Manufacturer Part Number: ST10F273M-4T3
• Description: MCU 16BIT 512K FLASH 144-LQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F273M-4T3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 36K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Processor Series: ST10F27x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F273M
(sampled voltage on C
must be designed to respect the following relation:
The formula above provides constraints for external network design, in particular on a
resistive path.
A second aspect involving the capacitance network must be considered. Assuming the three
capacitances C
equivalent circuit reported in
close), a charge-sharing phenomena is installed.
Figure 42. Charge-sharing timing diagram during sampling phase
In particular two different transient periods can be distinguished (see
●
A first and quick charge transfer from the internal capacitance C
sampling capacitance C
considering a worst case (since the time constant in reality would be faster) in which
C
C
This relation can again be simplified considering only C
condition. In reality, the transient is faster, but the A/D converter circuitry has been
designed to be robust also in the very worst case: the sampling time T
longer than the internal time constant:
The charge of C
voltage V
P2
S
are in series, and the time constant is:
V
is reported in parallel to C
V
V
V
CS
A
A2
A1
A1
1
F
, C
on the capacitance according to the following equation:
P1
Voltage Transient on C
P1
and C
S
) and the sum of R
and C
V A1
2
V A
P2
S
Figure
⋅
P2
(
⋅
initially charged at the source voltage V
occurs (C
C S
R S
----------------------------------------------------------------------------- -
τ 1
τ
is redistributed also on C
1
+
<
=
+
P1
C P1
41), when the sampling phase is started (A/D switch
(
(
R F
R
R SW
(call C
SW
+
S
+
S
+
R L
is supposed initially completely discharged):
C P2
S
R EQ
+
R
T
+ R
P
R AD
AD
+
S
= C
)
R SW
) C
F
=
⋅
∆V < 0.5 LSB
t
)
+ R
P1
⋅
V A
s
---------------------- -
C P
C P C S
+
< <
+ C
L
⋅
R AD
+
(
+ R
⋅
C P1
P2
C S
τ
τ
T
1
2
S
SW
), the two capacitances C
s
<
, determining a new value of the
< (R
= R
S
+
1
-- - LSB
2
+ R
as an additional worst
C P2
L
SW
(C
Electrical characteristics
AD
S
+ R
)
+ C
, the external circuit
P1
Figure
AD
A
P1
and C
(refer to the
) C
+ C
S
S
is always much
<< T
42):
P2
P2
)
S
to the
P
143/182
and