ST10F273M-4T3 STMicroelectronics, ST10F273M-4T3 Datasheet - Page 29

• Manufacturer Part Number: ST10F273M-4T3
• Description: MCU 16BIT 512K FLASH 144-LQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F273M-4T3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 36K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Processor Series: ST10F27x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F273M
Table 5.
1. A single bank is implemented but the last two sectors can be seen as a Bank 1 in order to maintain
Table 5
When Bootstrap mode is entered:
●
●
●
●
In Bootstrap mode, by default ROMS1 = 0, so the first 32 Kbytes of IFlash are mapped in
segment 0.
Example:
In default configuration, to program address 0, the user must put the value 0x01 0000 in the
FARL and FARH registers but to verify the content of the address 0, a read to 0x00 0000
must be performed.
The next
be addressed by the CPU .
Bank
compatibility with the Flash Programming routines developed for the ST10F273E (based on ST10F276E).
This means that the Control and Status flags for the blocks B0F10 and B0F11 are duplicated to also be
accessible as blocks B1F0 and B1F1.
B0
Test-Flash is seen and available for code fetches (address 0x00 0000)
User IFlash is only available for read and write accesses
Write accesses must be made with addresses starting in segment 1 from 0x01 0000,
whatever ROMS1 bit in SYSCON value
Read accesses are made in segment 0 or in segment 1 depending of ROMS1 value.
above refers to the configuration when bit ROMS1 of SYSCON register is set.
Table 6
Flash module sectorization (write operations, or ROMS1 = ‘1’)
Bank 0 Flash 10 (B0F10 / B1F0)
Bank 0 Flash 11 (B0F11 / B1F1)
shows the Control Register interface composition: This set of registers can
Bank 0 Test-Flash (B0TF)
Bank 0 Flash 0 (B0F0)
Bank 0 Flash 1 (B0F1)
Bank 0 Flash 2 (B0F2)
Bank 0 Flash 3 (B0F3)
Bank 0 Flash 4 (B0F4)
Bank 0 Flash 5 (B0F5)
Bank 0 Flash 6 (B0F6)
Bank 0 Flash 7 (B0F7)
Bank 0 Flash 8 (B0F8)
Bank 0 Flash 9 (B0F9)
Description
(1)
(1)
0x01 8000 - 0x01 FFFF
0x02 0000 - 0x02 FFFF
0x03 0000 - 0x03 FFFF
0x04 0000 - 0x04 FFFF
0x05 0000 - 0x05 FFFF
0x06 0000 - 0x06 FFFF
0x07 0000 - 0x07 FFFF
0x08 0000 - 0x08 FFFF
0x00 0000 - 0x00 0FFF
0x01 0000 - 0x01 1FFF
0x01 2000 - 0x01 3FFF
0x01 4000 - 0x01 5FFF
0x01 6000 - 0x01 7FFF
Addresses
Internal Flash memory
Size (bytes)
32 K
64 K
64 K
64 K
64 K
64 K
64 K
64 K
8 K
4 K
8 K
8 K
8 K
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