ST10F269Z2Q6/TR STMicroelectronics, ST10F269Z2Q6/TR Datasheet - Page 150

• Manufacturer Part Number: ST10F269Z2Q6/TR
• Description: MCU 16BIT 256KBIT FLASH 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F269Z2Q6/TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• Processor Series: ST10F26x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SSC, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

The real minimum value for TCL depends on the
jitter of the PLL. The PLL tunes f
locked on f
the maximum when it is referred to one TCL
period. It decreases according to the formula and
to the Figure 69 given below. For N periods of TCL
the minimum value is computed using the
corresponding deviation D
Figure 69 : Approximated Maximum PLL Jitter
21.4.8 - External Clock Drive XTAL1
V
Notes: 1. Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal. 25MHz is the maximum input
150/184
Oscillator period
High time
Low time
Rise time
Fall time
DD
= 5V
frequency when using an external crystal oscillator. However, 40MHz can be applied with an external clock source.
2. The input clock signal must reach the defined levels V
±4
±3
±2
±1
Parameter
TCL
Max.jitter [%]
XTAL
10%, V
MIN
2
D
. The relative deviation of TCL is
N
=
=
4
SS
TCL
4 N 15 %
= 0V, T
–
NOM
N
t
t
t
t
t
OSC
1
2
3
4
Symbol
:
A
8




= -40 to +125 °C (PQFP144 devices)
1
SR
SR
SR
SR
SR
–
- - - - - - - - - - - - -
CPU
100
D
N
min
25
10
10




to keep it
f
–
–
CPU
1
2
2
16
= f
XTAL
IL
max
3
3
and V
–
–
–
2
2
IH2
This approximated formula is valid for
1
where N = number of consecutive TCL periods
and 1
(N = 3):
D
3TCL
3TCL
3TCL
This is especially important for bus cycles using
wait states and e.g. for the operation of timers,
serial interfaces, etc. For all slower operations and
longer periods (e.g. pulse train generation or
measurement, lower
deviation caused by the PLL jitter is negligible.
.
3
N
f
12.5
min
CPU
5
5
–
–
min
min
min
2
2
40 and 10MHz
N
= f
XTAL
40. So for a period of 3 TCL periods
=
=
=
=
=
max
3
3
–
–
–
/ 2
2
2
4 - 3/15 = 3.8%
3TCL
3TCL
36.075ns (at f
45.1ns (at f
F = 1.5/2,/2.5/3/4/5
40 x N
f
NOM
NOM
10
10
min
CPU
Baud rates, etc.) the
f
–
–
CPU
32
2
2
= f
x (1 - 3.8/100)
x 0.962
CPU
XTAL
N
CPU
40MHz
100 x N
max
= 32MHz)
3
3
x F
–
–
2
2
= 40MHz)
ST10F269
Unit
ns
ns
ns
ns
ns