ST10F269Z2Q6/TR STMicroelectronics, ST10F269Z2Q6/TR Datasheet - Page 152

• Manufacturer Part Number: ST10F269Z2Q6/TR
• Description: MCU 16BIT 256KBIT FLASH 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F269Z2Q6/TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• Processor Series: ST10F26x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SSC, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

21.4.10 - Multiplexed Bus
V
ALE cycle time = 6 TCL + 2t
Table 46 : Multiplexed Bus Characteristics (PQFP144 devices)
152/184
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
22
23
25
27
38
39
40
DD
Symbol
= 5V
CC
CC
CC
CC
CC
CC
CC
CC
CC
SR
SR
SR
SR
SR
SR
CC
CC
CC
CC
CC
SR
CC
10%, V
ALE high time
Address setup to ALE
Address hold after ALE
ALE falling edge to RD, WR
(with RW-delay)
ALE falling edge to RD, WR (no
RW-delay)
Address float after RD, WR
(with RW-delay)
Address float after RD, WR
(no RW-delay)
RD, WR low time
(with RW-delay)
RD, WR low time
RD to valid data in
RD to valid data in
ALE low to valid data in
Address/Unlatched CS to valid
data in
Data hold after RD
rising edge
Data float after RD
Data valid to WR
Data hold after WR
ALE rising edge after RD, WR
Address/Unlatched CS hold
after RD, WR
ALE falling edge to Latched CS
Latched CS low to Valid Data In
Latched CS hold after RD, WR
(no RW-delay)
(with RW-delay)
(no RW-delay)
SS
Parameter
= 0V, T
A
+ t
A
= -40 to +125°C, C
C
+ t
F
(75ns at 40MHz CPU clock without wait states, PQFP144 devices).
1
1
1
1
15.5 + t
-8.5 + t
28 + t
10 + t
15 + t
10 + t
27 + t
4 + t
2 + t
4 + t
4 + t
-4 - t
4 + t
min.
Max. CPU Clock
–
–
–
–
–
–
0
–
–
A
A
A
A
F
A
C
C
F
F
F
= 40MHz
A
C
L
= 50pF,
18.5 + t
22 + 2t
18.5 + t
16.5 + t
+ t
10 - t
6 + t
max.
18.5
18.5
A
2t
t
–
–
–
–
–
6
–
–
–
–
–
–
–
–
C
+ t
A
C
A
A
C
C
C
F
+
+
3 TCL - 10.5 + t
2 TCL - 8.5 + t
TCL - 10.5 + t
2 TCL -9.5 + t
3 TCL -9.5 + t
2 TCL -15 + t
2 TCL -10 + t
2 TCL -15 + t
TCL - 8.5 + t
TCL - 8.5 + t
TCL - 8.5 + t
-8.5 + t
-4 - t
min.
1/2 TCL = 1 to 40MHz
Variable CPU Clock
–
–
–
–
–
–
0
–
–
A
A
A
A
A
C
F
F
C
C
A
F
F
2 TCL - 8.5 + t
2 TCL - 19 + t
3 TCL - 19 + t
3 TCL - 19
4 TCL - 28
3 TCL - 19
+ 2t
+ t
+ t
TCL + 6
10 - t
max.
C
A
A
–
–
–
–
–
6
–
–
–
–
–
–
–
–
+ 2t
+ t
+ t
A
ST10F269
C
C
A
C
C
F
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns