ST10F168SQ6 STMicroelectronics, ST10F168SQ6 Datasheet
ST10F168SQ6
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ST10F168SQ6 Summary of contents
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MCU WITH 256K BYTE FLASH MEMORY AND 8K BYTE RAM HIGH PERFORMANCE CPU – 16-BIT CPU WITH 4-STAGE PIPELINE – 80ns INSTRUCTION CYCLE TIME AT 25MHz CPU CLOCK – 400ns 16 X 16-BIT MULTIPLICATION – 800ns 32 / 16-BIT ...
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ST10F168 TABLE OF CONTENT 1 INTRODUCTION ......................................................................................................... 2 PIN DATA ................................................................................................................... 3 FUNCTIONAL DESCRIPTION.................................................................................... 4 MEMORY ORGANIZATION........................................................................................ 5 FLASH MEMORY ....................................................................................................... 5.1 PROGRAMMING / ERASING WITH ST EMBEDDED ALGORITHM KERNEL ......... . 5.2 PROGRAMMING EXAMPLES .................................................................................... 5.3 FLASH MEMORY CONFIGURATION........................................................................ ...
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SPECIAL FUNCTION REGISTER OVERVIEW.......................................................... 19.1 IDENTIFICATION REGISTERS .................................................................................. 20 ELECTRICAL CHARACTERISTICS .......................................................................... 20.1 ABSOLUTE MAXIMUM RATINGS .............................................................................. 20.2 PARAMETER INTERPRETATION.............................................................................. 20.3 DC CHARACTERISTICS ............................................................................................ 20.4 A/D CONVERTER CHARACTERISTICS .................................................................... 20.5 AC CHARACTERISTICS............................................................................................. 20.5.1 Test Waveforms ........................................................................................................ 20.5.2 Definition of ...
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ST10F168 1 - INTRODUCTION The ST10F168 is a derivative of the STMicroelec- tronics 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 12.5 million instructions per second) with high Figure 1 : Logic Symbol XTAL1 XTAL2 RSTIN RSTOUT ...
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PIN DATA Figure 2 : Pin Configuration (top view) 1 P6.0/CS0 2 P6.1/CS1 3 P6.2/CS2 4 P6.3/CS3 5 P6.4/CS4 6 P6.5/HOLD P6.6/HLDA 7 8 P6.7/BREQ P8.0/CC16IO 9 P8.1/CC17IO 10 11 P8.2/CC18IO P8.3/CC19IO 12 13 P8.4/CC20IO 14 P8.5/CC21IO P8.6/CC22IO ...
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ST10F168 Table 1 : Pin Description Symbol Pin Type P6 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver ...
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Table 1 : Pin Description (continued) Symbol Pin Type P2.0 - P2.7 47-54 I/O 16-bit bidirectional I/O port, bit-wise programmable for input or output via direction P2.8 - P2.15 57-64 bit. Programming an I/O pin as input forces the corresponding ...
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ST10F168 Table 1 : Pin Description (continued) Symbol Pin Type P4.0 - P4.7 85-92 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to ...
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Table 1 : Pin Description (continued) Symbol Pin Type P1L.0 - P1L.7 118-125 I/O Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or P1H.0 - P1H.7 128-135 output via direction bit. Programming an I/O pin as ...
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ST10F168 3 - FUNCTIONAL DESCRIPTION The architecture of the ST10F168 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. Figure 3 : Block Diagram 256K Byte Flash memory 6K Byte XRAM CAN_RxD P4.5 CAN CAN_TxD P4.6 ...
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MEMORY ORGANIZATION The memory space of the ST10F168 is configured in a Von Neumann architecture. Code memory, data memory, registers and I/O ports are orga- nized within the same linear address space of 16M Byte. The entire memory ...
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ST10F168 Figure 4 : ST10F168 on-chip memory mapping 0x14 0x5’0000 0x4’FFFF 0x13 0x4’C000 0x12 0x4’8000 0x11 0x4’4000 Bank 3 : 96K Byte 0x10 0x4’0000 0x0F 0x3’C000 0x0E 0x3’8000 0x3’7FFF 0x0D 0x3’4000 0x0C 0x3’0000 0x0B 0x2’C000 Bank 2 : 96K Byte ...
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FLASH MEMORY The ST10F168 provides 256K Byte of an electrically erasable and reprogrammable Flash Memory on-chip. The Flash Memory can be used both for code and data storage organized into four 32-bit wide blocks allowing even ...
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ST10F168 5.1 - Programming / Erasing with ST Embedded Algorithm Kernel There are three stages to run STEAK : – To load the registers with the STEAK command, the address and the data to be pro- gramed, ...
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Table 6 : Error Code Definition (R0 content after STEAK execution) Error Code 00h Operation was successful 01h Flash Protection is active 02h Vpp voltage not present 03h Programming operation failed 04h Address value (R1) incorrect: not in Flash address ...
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ST10F168 5.2 - Programming Examples Programming a double Word ; code shown below assumes that Flash is mapped in segment 1 ; ie. bit ROMS1 = ‘1’ in SYSCON register ; Flash must be enabled, ie. bit ROMEN = ‘1’ ...
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Programming a block of data The following code is provided as an example to program a block of data. Flash to be programmed is from address 01’9000h to 01’9FFEh (included). Source data (data to be copied into flash) is located ...
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ST10F168 5.3 - Flash Memory Configuration The default memory configuration ST10F168 Memory is determined by the state of the EA pin at reset. This value is stored in the Internal ROM Enable bit : ROMEN of the SYSCON Register. When ...
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CENTRAL PROCESSING UNIT (CPU) The CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedi- cated SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and ...
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ST10F168 6.1 - Instruction Set Summary The Table 8 lists the instructions of the ST10F168. The various addressing modes, instruction opera- tion, parameters for conditional execution of Table 8 : Instruction set summary Mnemonic ADD(B) Add Word (Byte) operands ADDC(B) ...
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Table 8 : Instruction set summary Mnemonic JNBS Jump relative and set bit if direct bit is not set CALLA, CALLI, CALLR Call absolute / indirect / relative subroutine if condition is met CALLS Call absolute subroutine in any code ...
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ST10F168 7 - EXTERNAL BUS CONTROLLER All external memory accesses are performed by the on-chip external bus controller. The EBC can be programmed to single chip mode when no external memory is required one of four dif- ferent ...
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INTERRUPT SYSTEM The interrupt response time for internal program execution is from 157ns to 375ns at 32MHz CPU clock. The ST10F168 architecture supports several mechanisms for fast and flexible response to ser- vice requests that can be generated ...
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ST10F168 Table 9 : Interrupt sources (continued) Source of Interrupt or PEC Service Request CAPCOM Register 18 CAPCOM Register 19 CAPCOM Register 20 CAPCOM Register 21 CAPCOM Register 22 CAPCOM Register 23 CAPCOM Register 24 CAPCOM Register 25 CAPCOM Register ...
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Hardware traps are exceptions or error conditions that arise during run-time. They cause immediate non-maskable system reaction similar to a stan- dard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified ...
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ST10F168 9 - CAPTURE / COMPARE (CAPCOM) UNIT The ST10F168 has two 16 channel CAPCOM units which support generation and control of timing sequences channels with a maximum resolution of 320ns at 32MHz CPU clock. The ...
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Table 12 : CAPCOM timer input frequencies, resolution and periods f = 25MHz CPU 000b 001b f pre-scaler 8 CPU Input Frequency 3.125MHz 1.56MHz Resolution 320ns 640ns Period 21.0ms 41.9ms Table 13 : CAPCOM Channels Pin Assignement CAPCOM Channel 0 ...
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ST10F168 10 - GENERAL PURPOSE TIMER UNIT The GPT unit is a flexible multifunctional timer / counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or ...
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The state of this latch may be used to clock timer T5 may be output on a port pin (T6OUT). The overflows / underflows of timer T6 can also be used to clock the CAPCOM timers T0 or ...
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ST10F168 Figure 7 : Block Diagram of GPT2 T5EUD CPU Clock T5 2n n=2...9 Mode T5IN Control CAPIN T6IN T6 Mode CPU Clock 2n n=2...9 Control T6EUD 30/74 U/D GPT2 Timer T5 Clear Capture GPT2 CAPREL Reload Toggle FF GPT2 ...
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PWM MODULE The pulse width modulation module can generate up to four PWM output signals using edge-aligned or centre-aligned PWM. In addition, the PWM module can generate PWM burst signals and sin- Table 16 : PWM unit frequencies ...
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ST10F168 12 - PARALLEL PORTS The ST10F168 provides up to 111 I/O lines organized into eight input / output ports and one input port. All port lines are bit-addressable, and all input / output lines are individually (bit-wise) programmable as ...
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A/D CONVERTER A10-bit A/D converter with 16 multiplexed input channels and a sample and hold circuit is integrated on-chip. The sample time (for loading the capacitors) and the conversion time is programmable and can be adjusted to the ...
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ST10F168 14 - SERIAL CHANNELS Serial communication with other microcontrollers, processors, terminals or external peripheral com- ponents is provided by two serial interfaces: the asynchronous / synchronous serial channel (ASC0) and the high-speed synchronous serial channel (SSC). Two dedicated Baud ...
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High Speed Synchronous Serial Channel (SSC) The High-Speed Synchronous Serial Interface SSC provides flexible high-speed serial communi- cation between the ST10F168 and other microcon- trollers, microprocessors or external peripherals. The SSC supports full-duplex and half-duplex syn- chronous communication; The serial ...
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ST10F168 15 - CAN MODULE The integrated CAN module completely handles the autonomous transmission and the reception of CAN frames according to the CAN specification V2.0 part B (active). The on-chip CAN module can receive and transmit standard frames with ...
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SYSTEM RESET Table 21 : Reset event definition Reset Source Power-on reset Long Hardware reset (synchronous & asynchronous) Short Hardware reset (synchronous reset) Watchdog Timer reset Software reset System reset initializes the MCU in a predefined state. There ...
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ST10F168 17.2 - Synchronous Reset (Warm Reset) A synchronous reset is triggered when is pulled low while V pin is at high level. In order PP to properly activate the internal reset logic of the MCU, the RSTIN pin must ...
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Figure 11 : Synchronous Warm Reset: Long low pulse on 4 TCL 12 TCL CPU Clock RSTIN V PP 200 A Discharge RSTOUT ALE Port0 Internal Reset Signal Notes: 1. RSTIN rising edge to internal latch of Port0 is 3CPU ...
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ST10F168 The simplest way to reset the ST10F168 is to insert a capacitor C1 between RSTIN and a capacitor between V pin and V PP with a pullup resistor R0 between The input provides an internal pullup ...
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The minimum reset circuit of Figure 14 is not ade- quate when the pin is driven from the RSTIN ST10F168 itself during software or watchdog trig- gered resets, because of the capacitor C1 that will keep the voltage on pin ...
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ST10F168 18 - POWER REDUCTION MODES Two different power reduction modes with different levels of power reduction can be entered under software control. In Idle mode the CPU is stopped, while the peripherals continue their operation. Idle mode can be ...
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SPECIAL FUNCTION REGISTER OVERVIEW Table 22 lists all SFRs which are implemented in the ST10F168 in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with ...
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ST10F168 Table 22 : Special Function Registers listed by name Physical 8-bit Name address address CC9IC b FF8Ah C5h CC10 FE94h 4Ah CC10IC b FF8Ch C6h CC11 FE96h 4Bh CC11IC b FF8Eh C7h CC12 FE98h 4Ch CC12IC b FF90h C8h ...
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Table 22 : Special Function Registers listed by name Physical 8-bit Name address address CC29IC b F184h E C2h CC30 FE7Ch 3Eh CC30IC b F18Ch E C6h CC31 FE7Eh 3Fh CC31IC b F194h E CAh CCM0 b FF52h A9h CCM1 ...
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ST10F168 Table 22 : Special Function Registers listed by name Physical 8-bit Name address address ODP6 b F1CEh E E7h ODP7 b F1D2h E E9h ODP8 b F1D6h E EBh ONES b FF1Eh 8Fh P0L b FF00h 80h P0H b ...
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Table 22 : Special Function Registers listed by name Physical 8-bit Name address address PWMIC b F17Eh E BFh RP0H b F108h E 84h S0BG FEB4h 5Ah S0CON b FFB0h D8h S0EIC b FF70h B8h S0RBUF FEB2h 59h S0RIC b ...
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ST10F168 Table 22 : Special Function Registers listed by name Physical 8-bit Name address address T6 FE48h 24h T6CON b FF48h A4h T6IC b FF68h B4h T7 F050h E 28h T78CON b FF20h 90h T7IC b F17Ah E BEh T7REL ...
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... A internal memory and size identifier, – Programming voltage description. IDMANUF (F07Eh / 3Fh MANUF R Description MANUF : Manufacturer Identifier - 020h: STmicroelectronics Manufacturer (JTAG worldwide normalisation). IDCHIP (F07Ch / 3Eh CHIPID R Description REVID : Device Revision Identifier - 1h for the first step, 2h for the second step,... ...
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ST10F168 20 - ELECTRICAL CHARACTERISTICS 20.1 - Absolute Maximum Ratings Symbol V Voltage on V pins with respect to ground Voltage on any pin with respect to ground IO I Input Current on any pin during overload ...
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Symbol Parameter I CC Input leakage current (all other) OZ2 I SR Overload current RSTIN pull-up resistor RST 5 I Read / Write inactive current RWH 7 I Read / Write active current RWL 6 6 ...
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ST10F168 Figure 15 : Supply / idle current as a function of operation frequency I [mA] 200 100 10 5 20.4 - A/D Converter Characteristics 10 0V, 4. -40, +85 C ...
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During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal resistance of the reference voltage source must allow the capacitance to reach its respective voltage level within t from the programmed conversion timing. 7. Partially ...
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ST10F168 20.5.2 - Definition of Internal Timing The internal operation of the ST10F168 is controlled by the internal CPU clock f edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of ...
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Prescaler Operation When pins P0.15-13 (P0H.7-5) equal ’001’ during reset, the CPU clock is derived from the internal oscillator (input clock signal 2:1 prescaler. The frequency half the frequency of CPU f and ...
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ST10F168 The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes f CPU locked The relative deviation of TCL is XTAL the maximum when it is refered to one TCL period. ...
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Memory Cycle Variables The tables below use three variables which are derived from the BUSCONx registers and which represent the special characteristics of the programmed memory cycle. The following table describes how these variables are computed. Symbol t ...
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ST10F168 Table 24 : Multiplexed bus characteristics (continued) Symbol Parameter t CC Data hold after ALE rising edge after RD Address / Unlatched CS hold 27 after RD ALE ...
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Figure 21 : External Memory Cycle : multiplexed bus, with / without read/write delay, normal ALE CLKOUT t 5 ALE t 6 CSx t 6 A23-A16 (A15-A8) BHE t Read Cycle 6m Address BUS (P0) RD Write Cycle Address BUS ...
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ST10F168 Figure 22 : External Memory Cycle: multiplexed bus, with / without read/write delay, extended ALE CLKOUT t 5 ALE CSx t 6 A23-A16 (A15-A8) BHE Read Cycle t 6 BUS (P0) Address RD Write Cycle ...
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Figure 23 : External Memory Cycle: multiplexed bus, with / without read/write delay, normal ALE, read/write chip select CLKOUT t 5 ALE t 6 A23-A16 (A15-A8) BHE t 6 Read Cycle Address BUS (P0) RdCSx t Write Cycle BUS (P0) ...
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ST10F168 Figure 24 : External Memory Cycle: multiplexed bus, with / without read/write delay, extended ALE, read/write chip select CLKOUT t 5 ALE t 6 A23-A16 (A15-A8) BHE Read Cycle t 6 BUS (P0) Address RdCSx Write Cycle BUS (P0) ...
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Demultiplexed Bus 10 0V, for Q6 version : ALE cycle time = 4 TCL + specified. Table 25 : Demultiplexed bus characteristics Symbol ...
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ST10F168 Table 25 : Demultiplexed bus characteristics (continued) Symbol Parameter t SR Latched CS low to Valid Data Latched CS hold after RD Address setup to RdCS, WrCS 82 (with RW-delay) t ...
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Figure 25 : External Memory Cycle: demultiplexed bus, with / without read/write delay, normal ALE CLKOUT t 5 ALE t 6 CSx A23-A16 (A15-A8) BHE Read Cycle Data Bus (P0 Write Cycle Data Bus (P0 ...
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ST10F168 Figure 26 : External Memory Cycle: demultiplexed bus, with / without read/write delay, extended ALE CLKOUT t 5 ALE CSx t 6 A23-A16 (A15-A8) BHE Read Cycle Data Bus (P0) RD Write Cycle Data Bus ...
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Figure 27 : External Memory Cycle: demultiplexed bus, with / without read/write delay, normal ALE, read/write chip select CLKOUT t 5 ALE A23-A16 (A15-A8) BHE Read Cycle Data Bus (P0 RdCsx Write Cycle Data Bus (P0 ...
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ST10F168 Figure 28 : External Memory Cycle: demultiplexed bus, no read/write delay, extended ALE, read/write chip select CLKOUT t 5 ALE t 6 A23-A16 (A15-A8) BHE Read Cycle Data Bus (P0) RdCsx Write Cycle Data Bus (P0) WrCSx 68/74 t ...
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CLKOUT and READY 10 0V, for Q6 version : unless otherwise specified Table 26 : CLKOUT and READY characteristics Symbol Parameter t CC CLKOUT cycle time CLKOUT ...
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ST10F168 Figure 29 : CLKOUT and READY Running cycle CLKOUT ALE RD, WR Synchronous READY Asynchronous READY 3) Notes: 1. Cycle as programmed, including MCTC wait states (Example shows ...
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External Bus Arbitration 10 0V, for Q6 version : unless otherwise specified. Symbol Parameter t SR HOLD input setup time to CLKOUT CLKOUT to HLDA high or ...
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ST10F168 Figure 31 : External bus arbitration, (regaining the bus) CLKOUT HOLD HLDA t 62 BREQ CSx (P6.x) Others Notes: 1. This is the last opportunity for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the ...
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PACKAGE MECHANICAL DATA Package Outline PQFP144 (28 x 28mm) Figure 32 : 144 Millimeters Dimensions Minimum A A1 0.25 A2 3.17 B 0.22 c 0.13 D 30.95 D1 27. 30.95 E1 27.90 ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied ...