ST10F168SQ6 STMicroelectronics, ST10F168SQ6 Datasheet - Page 56

• Manufacturer Part Number: ST10F168SQ6
• Description: MCU 256KB FLASH 12K RAM 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F168SQ6

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-MQFP, 144-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ST10F168
The real minimum value for TCL depends on the
jitter of the PLL. The PLL tunes f
locked on f
the maximum when it is refered to one TCL
period. It decreases according to the formula and
to the Figure 19 given below. For N periods of TCL
the minimum value is computed using the
corresponding deviation D
Figure 19 : Approximated maximum PLL jitter
20.5.8 - External Clock Drive XTAL1
V
otherwise specified.
Notes: 1. Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal.
Figure 20 : External clock drive XTAL1
56/74
DD
t
OSC
Symbol
t
t
t
t
1
2
3
4
= 5V
2. The input clock signal must reach the defined levels V
SR Oscillator period
SR High time
SR Low time
SR Rise time
SR Fall time
TCL
XTAL
10%, V
Max.jitter [%]
MIN
D
. The relative deviation of TCL is
N
=
=
SS
T CL
4 N 15 %
Parameter
= 0V, for Q6 version : T
4
3
2
1
–
NO M
N
:
2
t
1
4
1
–
CPU
---------- ---
100
D
N
8
to keep it
V
Min.
40
18
18
f
IL
CPU
–
–
A
1
2
2
= -40, +85 C and for Q3 version T
IL
= f
t
2
and V
t
3
XTAL
Max.
1000
10
10
–
–
2
2
IH2
16
where N = number of consecutive TCL periods
and 1
(N = 3):
D
3TCL
3TCL
This is especially important for bus cycles using wait
states and e.g. for the operation of timers, serial
interfaces, etc. For all slower operations and longer
periods (e.g. pulse train generation or measurement,
lower Baud rates, etc.) the deviation caused by the
PLL jitter is negligible (see Figure 19).
.
3
f
This approximated formula is valid for
t
CPU
Min.
OSC
1 < N < 40 and 10MHz < f
6
6
20
V
min
min
–
–
IH2
2
2
= f
N
= 4 - 3/15 = 3.8%
= 3TCL
= 3TCL
= (57.72ns at f
XTAL
Max.
40. So for a period of 3 TCL periods
500
6
6
–
–
3
2
/ 2
NOM
NOM
N = 1.5 / 2 / 2.5 / 3 / 4 / 5
40 x N
Min.
10
10
f
CPU
–
–
x (1 - 3.8/100)
x 0.962
2
2
A
CPU
CPU
= -40, + 125 C, unless
= f
t
4
< 25MHz.
32
XTAL
= 25MHz)
100 x N
Max.
x N
10
10
–
–
N
2
2
Unit
ns
ns
ns
ns
ns