TMP86FH12MG(Z) Toshiba, TMP86FH12MG(Z) Datasheet
TMP86FH12MG(Z)
Specifications of TMP86FH12MG(Z)
Related parts for TMP86FH12MG(Z)
TMP86FH12MG(Z) Summary of contents
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Bit Microcontroller TLCS-870/C Series TMP86FH12MG ...
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... Unintended Usage of Toshiba products listed in this document shall be made at the customer's own risk. 021023_B The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations ...
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Date Revision 2005/10/26 1 2006/4/21 2 2006/6/29 3 2006/10/17 4 Revision History First Release Contents Revised Periodical updating.No change in contents. Contents Revised ...
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...
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Table of Contents TMP86FH12MG 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Undefined Instruction Interrupt (INTUNDEF 3.6 Address Trap Interrupt (INTATRAP) . ...
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Timer/Counter (TC7) 9.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Timer Mode (TC3 and 4) .......................................................................................................... 125 11.3.6 16-Bit Event Counter Mode (TC3 and 4) ............................................................................................ 126 11.3.7 16-Bit Pulse Width Modulation (PWM) Output Mode (TC3 and 4)...................................................... 126 11.3.8 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 ...
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Register Setting ................................................................................................................................ 158 14.4 STOP/SLOW Modes during AD Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.5 ...
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Checksum (SUM ...
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... The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by impli- cation or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C • ...
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Features Emargency stop pin 7. 16-bit timer counter Timer, External trigger, Window, Pulse width measurement, Event counter, Programmable pulse generate (PPG) modes 8. 8-bit timer counter : Timer, Event counter, Programmable divider output ...
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Pin Assignment ( INT5 (TC1/INT4) P14 (BOOT/RXD) P01 VSS P37 (AIN7 XIN P36 (AIN6/STOP3 XOUT P35 (AIN5/STOP2 TEST P34 (AIN4/STOP1 VDD P33 (AIN3/STOP0 (XTIN) P21 P32 (AIN2 ...
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Block Diagram 1.3 Block Diagram Figure 1-2 Block Diagram Page 4 TMP86FH12MG ...
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Pin Names and Functions The TMP86FH12MG has MCU mode, parallel PROM mode, and serial PROM mode. Table 1-1 shows the pin functions in MCU mode. The serial PROM mode is explained later in a separate chapter. Table 1-1 Pin ...
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Pin Names and Functions Table 1-1 Pin Names and Functions(2/2) Pin Name P36 AIN6 STOP3 P35 AIN5 STOP2 P34 AIN4 STOP1 P33 AIN3 STOP0 P32 AIN2 P31 AIN1 INT0 P30 AIN0 EMG XIN XOUT RESET TEST VDD VSS Pin ...
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Operational Description 2.1 CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, and the reset ...
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System Clock Controller 2.1.3 Data Memory (RAM) The TMP86FH12MG has 512bytes (Address 0040H to 023FH) of internal RAM. The first 192 bytes (0040H to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations ...
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High-frequency clock XIN XOUT XIN (a) Crystal/Ceramic (b) External oscillator resonator Figure 2-3 Examples of Resonator Connection Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with dis- abling all interrupts and watchdog ...
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System Clock Controller 2.2.2 Timing Generator The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware from the basic clock (fc or fs). The timing generator provides the following functions. 1. Generation of ...
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Timing Generator Control Register TBTCR (0036H) (DVOEN) (DVOCK) Selection of input to the 7th stage DV7CK of the divider Note 1: In single clock mode, do not set DV7CK to “1”. Note 2: Do not set “1” ...
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System Clock Controller (2) IDLE1 mode In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are halted; however on-chip peripherals remain active (Operate using the high-frequency clock). IDLE1 mode is started by SYSCR2<IDLE> ...
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Switching back and forth between SLOW1 and SLOW2 modes are performed by SYSCR2<XEN>. In SLOW1 and SLEEP modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. ...
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System Clock Controller IDLE1 mode (a) Single-clock mode IDLE2 mode SLEEP2 mode SLEEP1 mode (b) Dual-clock mode Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1 and IDLE2 are called ...
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System Control Register 1 SYSCR1 (0038H) STOP RELM RETM OUTEN STOP STOP mode start Release method for STOP RELM mode Operating mode after STOP RETM mode OUTEN Port output during STOP mode Warm-up time at releasing WUT ...
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System Clock Controller 2.2.4 Operating Mode Control 2.2.4.1 STOP mode STOP mode is controlled by the system control register 1, the (STOP3 to STOP0) which is controlled by the STOP mode release control register (STOPCR). The pin is also ...
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Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt. PINT5: TEST (P2PRD). 0 JRS F, SINT5 LD (SYSCR1), 01010000B DI SET (SYSCR1). 7 SINT5: RETI STOP pin XOUT pin NORMAL operation Confirm by program that the STOP ...
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System Clock Controller STOP mode is released by the following sequence the dual-clock mode, when returning to NORMAL2, both the high-frequency and low warm-up period is inserted to allow oscillation time to stabilize. During warm ...
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Figure 2-9 STOP Mode Start/Release Page 19 TMP86FH12MG ...
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System Clock Controller 2.2.4.2 IDLE1/2 mode and SLEEP1/2 mode IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following status is maintained during these modes. 1. Operation of the CPU and ...
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Start the IDLE1/2 and SLEEP1/2 modes After IMF is set to "0", set the individual interrupt enable flag (EF) which releases IDLE1/2 and SLEEP1/2 modes. To start IDLE1/2 and SLEEP1/2 modes, set SYSCR2<IDLE> to “1”. • Release the IDLE1/2 ...
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System Clock Controller Figure 2-11 IDLE1/2 and SLEEP1/2 Modes Start/Release Page 22 TMP86FH12MG ...
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IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes. 1. Timing ...
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System Clock Controller • Start the IDLE0 and SLEEP0 modes • Release the IDLE0 and SLEEP0 modes of TBT and TBTCR<TBTEN>. cleared to “0” and the operation mode is returned to the mode preceding IDLE0 and SLEEP0 modes. Before ...
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Figure 2-13 IDLE0 and SLEEP0 Modes Start/Release Page 25 TMP86FH12MG ...
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System Clock Controller 2.2.4.4 SLOW mode SLOW mode is controlled by the system control register 2 (SYSCR2). The following is the methods to switch the mode with the warm-up counter. (1) Switching from NORMAL2 mode to SLOW1 mode First, ...
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Switching from SLOW1 mode to NORMAL2 mode First, set SYSCR2<XEN> to turn on the high-frequency oscillation. When time for stabilization (Warm up) has been taken by the timer/counter (TC4,TC3), clear SYSCR2<SYSCK> to switch the main system clock to the ...
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System Clock Controller Figure 2-14 Switching between the NORMAL2 and SLOW Modes Page 28 TMP86FH12MG ...
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Reset Circuit The TMP86FH12MG has four types of reset generation procedures: An external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and ...
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Reset Circuit 2.3.2 Address trap reset If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (when WDTCR1<ATAS> is set to “1”), DBR or ...
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Page 31 TMP86FH12MG ...
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Reset Circuit Page 32 TMP86FH12MG ...
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Interrupt Control Circuit The TMP86FH12MG has a total of 22 interrupt sources excluding reset. Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest are maskable. Interrupt sources are provided with interrupt ...
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Interrupt latches (IL28 to IL2) 3.1 Interrupt latches (IL28 to IL2) An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the unde- fined instruction interrupt. When interrupt request is generated, the ...
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Individual interrupt enable flags (EF28 to EF4) Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding bit of an individual interrupt enable flag to “1” enables acceptance of its interrupt, and setting ...
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Interrupt enable register (EIR) Interrupt Latches 15 14 ILH,ILL (003DH, 003CH) − IL14 15 14 ILD,ILE (002FH, 002EH) − − IL28 to IL2 Note 1: To clear any one of bits IL7 to IL4, be sure to write "1" ...
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Interrupt Sequence An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to “0” by resetting or an instruction. Interrupt acceptance sequence requires 8 machine cycles (2 µs @16 MHz) after ...
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Interrupt Sequence A maskable interrupt is not accepted until the IMF is set to “1” even if the maskable interrupt higher than the level of current servicing interrupt is requested. In order to utilize nested interrupt service, the IMF ...
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Example :Save/store register using data transfer instructions PINTxx: LD (interrupt processing) LD RETI Main task Saving/Restoring general-purpose registers using PUSH/POP data transfer instruction Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing 3.3.3 Interrupt return Interrupt return instructions [RETI]/[RETN] perform as ...
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Software Interrupt (INTSW) Example 2 :Restarting without returning interrupt (In this case, PSW (Includes IMF) before interrupt acceptance is discarded.) PINTxx: Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next inter- rupt ...
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External Interrupts The TMP86FH12MG has 6 external interrupt inputs. These inputs are equipped with digital noise reject circuits (Pulse inputs of less than a certain time are eliminated as noise). Edge selection is also possible with INT1 to INT4. ...
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External Interrupts External Interrupt Control Register EINTCR 7 (0037H) INT1NC INT0EN INT1NC INT0EN INT4 ES INT3 ES INT2 ES INT1 ES Note 1: fc: High-frequency clock [Hz], *: Don’t care Note 2: When the system clock frequency is switched ...
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Special Function Register (SFR) The TMP86FH12MG adopts the memory mapped I/O system, and all peripheral control and data transfers are per- formed through the special function register (SFR) or the data buffer register (DBR). The SFR is mapped on ...
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SFR Address 0026H 0027H 0028H 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH Note 1: Do not access reserved areas by the program. Note ...
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DBR Address 0F80H 0F81H 0F82H 0F83H 0F84H 0F85H 0F86H 0F87H 0F88H 0F89H 0F8AH 0F8BH 0F8CH 0F8DH 0F8EH 0F8FH 0F90H 0F91H 0F92H 0F93H 0F94H 0F95H 0F96H 0F97H 0F98H 0F99H 0F9AH 0F9BH 0F9CH 0F9DH 0F9EH 0F9FH Read Write SIOBR0 SIOBR1 SIOBR2 ...
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DBR Address 0FA0H 0FA1H 0FA2H 0FA3H 0FA4H 0FA5H 0FA6H 0FA7H 0FA8H 0FA9H 0FAAH 0FABH 0FACH 0FADH 0FAEH 0FAFH 0FB0H 0FB1H 0FB2H 0FB3H 0FB4H 0FB5H 0FB6H 0FB7H 0FB8H 0FB9H 0FBAH 0FBBH 0FBCH 0FBDH 0FBEH 0FBFH Address 0FC0H 0FDFH Read TC7CAPAL ...
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Address 0FE0H 0FE1H 0FE2H 0FE3H 0FE4H 0FE5H 0FE6H 0FE7H 0FE8H 0FE9H 0FEAH 0FEBH 0FECH 0FEDH 0FEEH 0FEFH 0FF0H 0FF1H 0FF2H 0FF3H 0FF4H 0FF5H 0FF6H 0FF7H 0FF8H 0FF9H 0FFAH 0FFBH 0FFCH 0FFDH 0FFEH 0FFFH Note 1: Do not access reserved areas ...
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DBR Page 48 TMP86FH12MG ...
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I/O Ports The TMP86FH12MG has 4 parallel input/output ports (24 pins) as follows. Primary Function Port P0 8-bit I/O port Port P1 5-bit I/O port Port P2 3-bit I/O port Port P3 8-bit I/O port Each output port contains ...
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Port P0 (P07 to P00) 5.1 Port P0 (P07 to P00) Port 8-bit input/output port. Port P0 is also used as an external interrupt input, a serial interface input/output, an UART input/output and a timer/counter input/output. ...
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STOP OUTEN P0OUTCRi P0OUTCRi (P0PRD) (P0DR) (P0DR) STOP OUTEN P0OUTCRj P0OUTCRj (P0PRD) (P0DR) Data output (P0DR) Note and and ...
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Port P0 (P07 to P00 P0DR P07 P06 (0000H) PPG2 PPG1 R/W INT2 INT1 P0OUTCR (0004H) P0OUTCR Port P0 output circuit control (Set for each bit individually) P0PRD P07 P06 (0008H) Read only ...
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Port P1 (P17 to P10) Port 5-bit input/output port which can be configured as an input or output in one-bit unit. Port P1 is also used as a timer/counter input/output, an external interrupt input and a ...
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Port P1 (P17 to P10 P1DR (0001H) R P1CR (0005H) P1CR I/O control for port P1 (Specified for each bit P14 P13 P12 P11 TC1 TC4 PPG DVO INT3 PWM4 ...
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Port P2 (P22 to P20) Port 3-bit input/output port also used as an external interrupt, a STOP mode release signal input, and low-frequency crystal oscillator con- nection pins. When used as an input port ...
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Port P3 (P37 to 30) 5.4 Port P3 (P37 to 30) Port 8-bit input/output port which can be configured as an input or output in one-bit unit. Port P3 is also used as an analog input, ...
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P3CR2i D Q P3CR2i P3CR1i D Q P3CR1i (P3DRi) (P3DRi STOP OUTTEN AINDS SAIN a) P37,P32 to P30 STOPkEN P3CR2j D Q P3CR2j P3CR1j D Q P3CR1j (P3DRj) (P3DRj STOP OUTTEN AINDS SAIN b) P36 to ...
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Port P3 (P37 to 30 P3DR P37 P36 (0003H) AIN7 AIN6 R/W STOP3 7 6 P3CR1 (0006H) P3CR1 I/O control for port P3 (Specified for each bit P3CR2 (0007H) P3CR2 P3 port input control (Specified ...
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Watchdog Timer (WDT) The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spu- rious noises or the deadlock conditions, and return the CPU to a system recovery routine. The ...
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Watchdog Timer Control 6.2 Watchdog Timer Control The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watch- dog timer is automatically enabled after the reset release. 6.2.1 Malfunction Detection Methods Using the Watchdog ...
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Watchdog Timer Control Register WDTCR1 (0034H) (ATAS) WDTEN Watchdog timer enable/disable Watchdog timer detection time WDTT [s] WDTOUT Watchdog timer output select Note 1: After clearing WDTOUT to “0”, the program cannot set it to “1”. ...
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Watchdog Timer Control 6.2.3 Watchdog Timer Disable To disable the watchdog timer, set the register in accordance with the following procedures. Setting the reg- ister in other procedures causes a malfunction of the microcontroller. 1. Set the interrupt master ...
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Watchdog Timer Reset When a binary-counter overflow occurs while WDTCR1<WDTOUT> is set to “1”, a watchdog timer reset request is generated. When a watchdog timer reset request is generated, the internal hardware is reset. The reset time is maximum ...
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Address Trap 6.3 Address Trap The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate address traps. Watchdog Timer Control Register WDTCR1 (0034H) Select address trap generation in ATAS ...
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Address Trap Reset While WDTCR1<ATOUT> is “1”, if the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”), DBR or the ...
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Address Trap Page 66 TMP86FH12MG ...
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Time Base Timer (TBT) The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base timer interrupt (INTTBT). 7.1 Time Base Timer 7.1.1 Configuration MPX 23 15 fc/2 or fs/2 21 ...
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Time Base Timer Note 2: The interrupt frequency (TBTCK) must be selected with the time base timer disabled (TBTEN="0"). (The interrupt fre- quency must not be changed with the disable from the enable state.) Both frequency selection and enabling ...
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Divider Output ( DVO Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. Divider output is from 7.2.1 Configuration Output latch D Q Data output MPX ...
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Divider Output (DVO) Example :1.95 kHz pulse output (fc = 16.0 MHz) Table 7-2 Divider Output Frequency ( Example : fc = 16.0 MHz 32.768 kHz ) DVOCK LD (TBTCR) , 00000000B LD (TBTCR) , 10000000B Divider ...
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Real-Time Clock The TMP86FH12MG include a real time counter (RTC). A low-frequency clock can be used to provide a periodic interrupt (0.0625[s],0.125[s],0.25[s],0.50[s programmed interval, implement the clock function. The RTC can be used in the mode in ...
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Function 8.3 Function The RTC counts up on the internal low-frequency clock. When RTCCR<RTCRUN> is set to “1”, the binary counter starts counting up. Each time the end of the period specified with RTCCR<RTCSEL> is detected, an INTRTC interrupt ...
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Timer/Counter (TC7) 9.1 Configuration fc/2 S TC7CK PPG2INI PPG1INI TC7CR1 TRGSEL NCRSEL Noise TC7 pin canceller CSIDIS Compare Compare register A register B TC7DRA TC7DRB EMG pin Figure ...
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Control Select a source clock TC7CK (Supplied to the up counter). Select the duration of noise elimination for NCRSEL TC7 input (after passing through the flip-flop). Specify the initial PPG1INI value of PPG1 out- put. Specify the initial PPG2INI ...
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TC7ST Start/stop the timer. Select the state when stopped. STM Select continuous or one-time output. Disable the first interrupt at upon a com- CSIDIS mand start. CNTBF Counting status flag EMGF Emergency output stop flag Note 1: The TC7CR1 and ...
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Control Dead Time 2 Setup Register 15 TC7DRD (0FB1H, 0FB0H) Read/Write (Initial value: **** **00 0000 0000) Pulse Width 2 Setup Register 15 TC7DRE (0FB3H, 0FB2H) Read/Write (Initial value: **** **00 0000 0000) Note 1: Data registers TC7DRA to ...
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Configuring Control and Data Registers Configure control and data registers in the following order: 1. Configure mode settings: TC7CR1, TC7CR2 2. Configure data registers (Dead time, pulse width): TC7DRA, TC7DRB, TC7DRD, TC7DRE (only those required for selected mode) 3. ...
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Features More than one data write A1 A2 TC7DRA B1 B2 TC7DRB C1 C2 TC7DRC Data valid a1 in each b1 period c1 Period (1) Figure 9-3 Example Configuration of Control/data Registers (2) 9.4 Features 9.4.1 Programmable pulse generator ...
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When the value set in the TC7DRC is an odd number, the PPG2 pulse width is one count longer than the PPG1 pulse width. (b) Dead time TC7DRA: 000H ≤ TC7DRA < TC7DRC/2 To specify no dead time, set the ...
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Features (3) Valid range for data register values (a) Period: (b) Pulse width: (c) Dead time: Source clock S, 0 Counter Dead time Pulse width Period PPG1 output PPG2 output INTTC7T INTTC7P Figure 9-5 Example Operation in Variable Duty ...
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The PPG1 output is active at the beginning of a period, remains active during the pulse width spec- ified in the TC7DRB, after which it is inactive until the end of the period. The PPG2 output is active at the ...
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Features Source clock 0 Counter Dead time Pulse width Period Dead time Pulse width PPG1 output PPG2 output INTTC7T INTTC7P Figure 9-6 Example Operation in PPG1/PPG2 Independent Mode: Command and Capture Start, Positive Logic, Continuous Output 9.4.2 Starting a ...
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Register settings CSTC = “00”: Command start and capture mode STM: Continuous/one-time output TC7ST = “1”: Starts counting PPG1 Count start (Command) PPG output with a period specified with TC7DRC Figure 9-7 Example Operation in Command Start and Capture ...
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Features 9.4.2.3 Trigger start mode (1) Description If an edge specified with the start edge selection field (TRGSEL) appears on the TC7 pin, the timer starts counting. The counter is cleared and stopped while the TC7 pin is driven ...
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The captured data is first stored in the capture buffer. At the end of the period, the data is trans- ferred from the capture buffer to the capture register trigger input does not appear within a period, the ...
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Features TC7 input (Signal after noise elimination) Capture buffers Capture registers TC7 input (Signal after noise elimination) Capture buffers Capture registers Figure 9-10 Example Operation in Trigger Capture Mode 9.4.2.5 Trigger start/stop acceptance mode (1) Selecting an input signal ...
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TRGSEL = 0 Counter operating Counter stopped TC7 pin input Count Count cleared started Figure 9-11 Trigger Input Signal When TRGSEL is set select a falling-edge trigger, a falling edge detected on the TC7 pin causes the ...
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Features TC7 pin input PPG1 output (Positive logic) PPG2 output (Positive logic) INTTC7T INTTC7P Count started Figure 9-12 Start and Clear/stop Triggers on the TC7 Pin: Falling-edge Trigger (Counting stopped at high level), Triggers Always Accepted (3) Ignoring triggers ...
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Configuring how the timer stops Setting TC7ST to 0 causes the timer to stop with the specified output state according to the setting of STM. 9.4.3.1 Counting stopped with the outputs initialized When STM is set to 00, the ...
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Features PPG1 (Positive logic) PPG1INI = 0 PPG2 (Negative logic) PPG1INI = 1 Output enabled PPG1E/PPG2E = 1 Figure 9-14 Immediately Stopping and Clearing the Counter with the Outputs Initialized PPG1 (Positive logic) PPG1INI = 0 PPG2 (Negative logic) ...
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PPG output control (Initial value/output logic, enabling/disabling output) 9.4.5.1 Specifying initial values and output logic for PPG outputs The PPG1INI and PPG2INI bits (TC7CR1<PPG1INI> and TC7CR1<PPG2INI>) specify the initial val- ues of PPG1 and PPG2 outputs as well as ...
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Features Table 9-1 Noise Canceller Settings Sampling Frequency NCRSEL (Number of Samplings) 00 fc/4 (5) 01 fc/2 ( (5) 11 (None) TC7 input F/F fc fc/4 fc fc/2 fc/4 TC7 ...
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Note 1: If the pin input level changes while the specified noise elimination threshold is being modified, the noise canceller may assume noise as a pulse or cancel a pulse as noise. Note 2: If noise occurs in synchronization with ...
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Features If a command start is specified (1 is written in TC7ST) when the TC7 pin stop level, the counter does not start (INTTC7P does not occur); a subsequent trigger start edge causes the counter to ...
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EMG interrupt An EMG interrupt (INTEMG) occurs when an emergency PPG output stop input is accepted. To use an INTEMG interrupt for some processing, ensure that the interrupt is enabled beforehand. When the pin is low with EMGIE set ...
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Features Emergency stop input PPG pin output EMG pin input EMGIE EMGF (State monitor) EMG interrupt TC7ST STM Figure 9-23 Timing between 9.4.9 TC7 operation and microcontroller operating mode The TC7 operates when the microcontroller is placed in NORMAL1, ...
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TimerCounter 1 (TC1) 10.1 Configuration Figure 10-1 TimerCounter 1 (TC1) Page 97 TMP86FH12MG ...
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TimerCounter Control 10.2 TimerCounter Control The TimerCounter 1 is controlled by the TimerCounter 1 control register (TC1CR) and two 16-bit timer registers (TC1DRA and TC1DRB). Timer Register 15 14 TC1DRA (0011H, 0010H) TC1DRB (0013H, 0012H) TimerCounter 1 Control Register ...
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Note 4: Auto-capture can be used only in the timer, event counter, and window modes. Note 5: To set the timer registers, the following relationship must be satisfied. TC1DRA > TC1DRB > 1 (PPG output mode), TC1DRA > 1 (other ...
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Function 10.3 Function TimerCounter 1 has six types of operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output modes. 10.3.1 Timer mode In the timer mode, the up-counter counts up using the ...
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Timer start Source clock Counter 0 1 TC1DRA ? INTTC1 interruput request Source clock m − − 1 Counter m − 1 TC1DRB ? ACAP1 Figure 10-2 Timer Mode Timing Chart n − ...
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Function 10.3.2 External Trigger Timer Mode In the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the TC1 pin, and counts up at the edge of the internal clock. For the trigger edge ...
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Count start TC1 pin input Source clock Up-counter TC1DRA INTTC1 interrupt request Count start TC1 pin input Source clock Up-counter TC1DRA INTTC1 interrupt request Figure 10-3 External Trigger Timer Mode Timing Chart ...
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Function 10.3.3 Event Counter Mode In the event counter mode, the up-counter counts up at the edge of the input pulse to the TC1 pin. Either the rising or falling edge of the input pulse is selected as the ...
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Window Mode In the window mode, the up-counter counts up at the rising edge of the pulse that is logical ANDed product of the input pulse to the TC1 pin (window pulse) and the internal source clock. Either the ...
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Function 10.3.5 Pulse Width Measurement Mode In the pulse width measurement mode, the up-counter starts counting by the input pulse triggering of the TC1 pin, and counts up at the edge of the internal clock. Either the rising or ...
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Example :Duty measurement (resolution fc/2 CLR LD DI SET PINTTC1: CPL JRS RETI SINTTC1 RETI : VINTTC1: DW TC1 pin INTTC1 interrupt request INTTC1SW 7 [Hz]) (INTTC1SW INTTC1 ...
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Function Count start TC1 pin input Internal clock Counter TC1DRB INTTC1 interrupt request Count start TC1 pin input Internal clock Counter TC1DRB INTTC1 interrupt request Trigger (a) Single-edge capture 0 1 ...
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Programmable Pulse Generate (PPG) Output Mode In the programmable pulse generation (PPG) mode, an arbitrary duty pulse is generated by counting per- formed in the internal clock. To start the timer, TC1CR<TC1S> specifies either the edge of the input ...
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Function Example :Generating a pulse which is high-going for 800 µs and low-going for 200 µs ( MHz) LD LDW LDW LD Example :After stopping PPG, setting the PPG pin to a high-level to restart PPG (fc ...
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Timer start Internal clock Counter TC1DRB n Match detect TC1DRA m PPG pin output INTTC1 interrupt request Count start TC1 pin input Trigger Internal clock Counter TC1DRB m TC1DRA PPG pin output ...
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Function Page 112 TMP86FH12MG ...
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TimerCounter (TC3, TC4) 11.1 Configuration 11 3 fc fc/2 16-bit mode G fc TC4 pin H S TC4M ...
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Configuration 11.2 TimerCounter Control The TimerCounter 3 is controlled by the TimerCounter 3 control register (TC3CR) and two 8-bit timer registers (TTREG3, PWREG3). TimerCounter 3 Timer Register TTREG3 7 6 (0019H) R/W PWREG3 7 6 (0017H) R/W Note 1: ...
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Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 11- 3. Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the ...
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Configuration The TimerCounter 4 is controlled by the TimerCounter 4 control register (TC4CR) and two 8-bit timer registers (TTREG4 and PWREG4). TimerCounter 4 Timer Register TTREG4 7 6 (001AH) R/W PWREG4 7 6 (0018H Note 1: Do ...
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Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC3CR<TC3CK>. Set the timer start control and timer F/F control by programming TC4S and TFF4, respectively. Note 7: The operating clock settings are limited depending ...
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Configuration Table 11-3 Constraints on Register Values Being Compared Operating mode 8-bit timer/event counter 8-bit PDO 8-bit PWM 16-bit timer/event counter Warm-up counter 16-bit PWM 16-bit PPG Note Register Value 1≤ (TTREGn) ≤255 1≤ ...
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Function The TimerCounter 3 and 4 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8- bit pulse width modulation (PWM) output modes. The TimerCounter 3 and 4 (TC3, 4) are cascadable to form a 16- ...
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Configuration TC4CR<TC4S> Internal Source Clock Counter TTREG4 ? INTTC4 interrupt request 11.3.2 8-Bit Event Counter Mode (TC3 the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj ...
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Example :Generating 1024 Hz pulse using TC4 (fc = 16.0 MHz Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift ...
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Configuration Figure 11-4 8-Bit PDO Mode Timing Chart (TC4) Page 122 TMP86FH12MG ...
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Pulse Width Modulation (PWM) Output Mode (TC3, 4) This mode is used to generate a pulse-width modulated (PWM) signals with bits of resolution. The up-counter counts up using the internal clock. When a match between ...
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Configuration Figure 11-5 8-Bit PWM Mode Timing Chart (TC4) Page 124 TMP86FH12MG ...
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Timer Mode (TC3 and 4) In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 3 and 4 are cascad- able to form a 16-bit timer. When a match between the up-counter and the ...
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Configuration 11.3.6 16-Bit Event Counter Mode (TC3 and 4) In the event counter mode, the up-counter counts up at the falling edge to the TC3 pin. The TimerCounter 3 and 4 are cascadable to form a 16-bit event counter. ...
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CLR (TC4CR).3: Stops the timer. CLR (TC4CR).7 : Sets the Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered with- out stopping of the timer when fc, ...
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Configuration Figure 11-7 16-Bit PWM Mode Timing Chart (TC3 and TC4) Page 128 TMP86FH12MG ...
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Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 3 and 4 are cascad- able to enter the 16-bit PPG mode. The ...
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Configuration Figure 11-8 16-Bit PPG Mode Timing Chart (TC3 and TC40) Page 130 TMP86FH12MG ...
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Warm-Up Counter Mode In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. The timer counter 3 and 4 are cascadable to form a 16-bit ...
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Configuration 11.3.9.2 High-Frequency Warm-Up Counter Mode (SLOW1 → SLOW2 → NORMAL2 → NORMAL1) In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation sta- bility is obtained. Before starting the timer, ...
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Synchronous Serial Interface (SIO) The TMP86FH12MG has a clocked-synchronous 8-bit serial interface. Serial interface has an 8-byte transmit and receive data buffer that can automatically and continuously transfer bits of data. Serial interface is connected to ...
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Control 12.2 Control The serial interface is controlled by SIO control registers (SIOCR1/SIOCR2). The serial interface status can be determined by reading SIO status register (SIOSR). The transmit and receive data buffer is controlled by the SIOCR2<BUF>. The data ...
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WAIT Wait control Number of transfer words BUF (Buffer address in use) Note 1: The lower 4 bits of each buffer are used during 4-bit transfers. Zeros (0) are stored to the upper 4bits when receiving. Note 2: Transmitting starts ...
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Serial clock 12.3.1.1 Internal clock Any of six frequencies can be selected. The serial clock is output to the outside on the SCK pin. The SCK pin goes high when transfer starts. When data writing (in the transmit mode) ...
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Shift edge The leading edge is used to transmit, and the trailing edge is used to receive. 12.3.2.1 Leading edge Transmitted data are shifted on the leading edge of the serial clock (falling edge of the output). 12.3.2.2 Trailing ...
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Transfer Mode SCK pin SO pin INTSIO interrupt SCK pin SO pin INTSIO interrupt SCK pin SI pin INTSIO interrupt Figure 12-6 Number of words to transfer (Example: 1word = 4bit) 12.6 Transfer Mode SIOCR1<SIOM> is used to select ...
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SIOCR1<SIOS> is cleared, the operation will end after all bits of words are transmitted. That the transmission has ended can be determined from the status of SIOSR<SIOF> because SIOSR<SIOF> is cleared to “0” when a transfer is completed. When SIOCR1<SIOINH> ...
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Transfer Mode SCK pin SIOSR<SIOF> SO pin Figure 12-9 Transmiiied Data Hold Time at End of Transfer 12.6.2 4-bit and 8-bit receive modes After setting the control registers to the receive mode, set SIOCR1<SIOS> to “1” to enable receiving. ...
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SIOCR1<SIOS> SIOSR<SIOF> SIOSR<SEF> SCK pin (Output) SI pin INTSIO Interrupt DBR Figure 12-10 Receive Mode (Example: 8bit, 1word transfer, Internal clock) 12.6.3 8-bit transfer / receive mode After setting the SIO control register to the 8-bit ...
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Transfer Mode Note:The buffer contents are lost when the transfer mode is switched should become necessary to switch the transfer mode, end receiving by clearing SIOCR1<SIOS> to “0”, read the last data and then switch the trans- ...
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Asynchronous Serial interface (UART ) 13.1 Configuration UART control register 1 UARTCR1 3 2 INTTXD INTRXD S fc/ fc/26 C fc/52 fc/104 fc/208 fc/416 F INTTC3 G H fc/96 Baud rate generator Figure 13-1 ...
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Control 13.2 Control UART is controlled by the UART Control Registers (UARTCR1, UARTCR2). The operating status can be moni- tored using the UART status register (UARTSR). UART Control Register1 7 6 UARTCR1 (0021H) TXE RXE TXE Transfer operation RXE ...
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UART Status Register UARTSR (0021H) PERR FERR OERR RBFL PERR Parity error flag FERR Framing error flag OERR Overrun error flag RBFL Receive data buffer full flag TEND Transmit end flag TBEP Transmit data buffer empty ...
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Transfer Data Format 13.3 Transfer Data Format In UART, an one-bit start bit (Low level), stop bit (Bit length selectable at high level, by UARTCR1<STBT>), and parity (Select parity in UARTCR1<PE>; even- or odd-numbered parity by UARTCR1<EVEN>) are added ...
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Transfer Rate The baud rate of UART is set of UARTCR1<BRG>. The example of the baud rate are shown as follows. Table 13-1 Transfer Rate (Example) BRG 000 001 010 011 100 101 When TC3 is used as the ...
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STOP Bit Length 13.6 STOP Bit Length Select a transmit stop bit length (1 bit or 2 bits) by UARTCR1<STBT>. 13.7 Parity Set parity / no parity by UARTCR1<PE> and set parity type (Odd- or Even-numbered) by UARTCR1<EVEN>. 13.8 ...
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Status Flag 13.9.1 Parity Error When parity determined using the receive data bits differs from the received parity bit, the parity error flag UARTSR<PERR> is set to “1”. The UARTSR<PERR> is cleared to “0” when the RDBUF is read ...
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Status Flag UARTSR<RBFL> RXD pin Shift register RDBUF UARTSR<OERR> INTRXD interrupt Note:Receive operations are disabled until the overrun error flag UARTSR<OERR> is cleared. 13.9.4 Receive Data Buffer Full Loading the received data in RDBUF sets receive data buffer full ...
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TDBUF xxxx ***** 1 1xxxx0 Shift register TXD pin Start UARTSR<TBEP> INTTXD interrupt Figure 13-9 Generation of Transmit Data Buffer Empty 13.9.6 Transmit End Flag When data are transmitted and no data is in TDBUF (UARTSR<TBEP> = “1”), transmit end ...
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Status Flag Page 152 TMP86FH12MG ...
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AD Converter (ADC) The TMP86FH12MG have a 10-bit successive approximation type AD converter. 14.1 Configuration The circuit configuration of the 10-bit AD converter is shown in Figure 14-1. It consists of control register ADCCR1 and ADCCR2, converted value ...
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Register configuration 14.2 Register configuration The AD converter consists of the following four registers converter control register 1 (ADCCR1) This register selects the analog channels and operation mode (Software start or repeat) in which to per- form ...
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AD Converter Control Register ADCCR2 (0026H) IREFON DA converter (Ladder resistor) connection IREFON control AD conversion time select ACK (Refer to the following table about the con- version time) Note 1: Always set bit0 in ADCCR2 ...
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Register configuration EOCF ADBF Note 1: The ADCDR2<EOCF> is cleared to "0" when reading the ADCDR1. Therfore, the AD conversion result should be read to ADCDR2 more first than ADCDR1. Note 2: The ADCDR2<ADBF> is set to "1" when ...
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Function 14.3.1 Software Start Mode After setting ADCCR1<AMD> to “01” (software start mode), set ADCCR1<ADRS> to “1”. AD conver- sion of the voltage at the analog input pin specified by ADCCR1<SAIN> is thereby started. After completion of the AD ...
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Function ADCCR1<AMD> AD conversion start ADCCR1<ADRS> Conversion operation Indeterminate ADCDR1,ADCDR2 ADCDR2<EOCF> INTADC interrupt request ADCDR1 ADCDR2 14.3.3 Register Setting 1. Set up the AD converter control register 1 (ADCCR1) as follows: • Choose the channel to AD convert using ...
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Example :After selecting the conversion time 19.5 µ MHz and the analog input channel AIN3 pin, perform AD con- version once. After checking EOCF, read the converted value, store the lower 2 bits in address 0009EH nd store ...
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Analog Input Voltage and AD Conversion Result 14.5 Analog Input Voltage and AD Conversion Result The analog input voltage is corresponded to the 10-bit digital value converted by the AD as shown in Figure 14-4. 3FF H 3FE H ...
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... The internal equivalent circuit of the analog input pins is shown in Figure 14-5. The higher the output impedance of the analog input source, more easily they are susceptible to noise. Therefore, make sure the out- put impedance of the signal source in your design is 5 kΩ or less. Toshiba also recommends attaching a capac- itor external to the chip. ...
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Precautions about AD Converter Page 162 TMP86FH12MG ...
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Key-on Wakeup (KWU) In the TMP86FH12MG, the STOP mode is released by not only P20( STOP3) pins. When the STOP mode is released by STOP0 to STOP3 pins, the In details, refer to the following section " 15.2 Control ...
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Function Also, each level of the STOP0 to STOP3 pins can be confirmed by reading corresponding I/O port data register, check all STOP0 to STOP3 pins "H" that is enabled by STOPCR before the STOP mode is startd (Note2). ...
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... The parallel PROM mode allows the flash memory to be accessed as a stand-alone flash memory by the program writer provided by the third party. High-speed access to the flash memory is available by control- ling address and data signals directly. For the support of the program writer, please ask Toshiba sales rep- resentative. ...
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Flash Memory Control 16.1 Flash Memory Control The flash memory is controlled via the flash memory control register (FLSCR) and flash memory stanby control resister (FLSSTB). Flash Memory Control Register FLSCR 7 6 (0FFFH) Flash memory command sequence exe- ...
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Transfer the control program of the FLSSTB register to the RAM area. 2. Jump to the RAM area. 3. Disable (DI) the interrupt master enable flag (IMF = “0”). 4. Set FLSSTB<FSTB> to “1”. 5. Execute the user program. ...
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Command Sequence 16.2 Command Sequence The command sequence in the MCU and the serial PROM modes consists of six commands (JEDEC compatible), as shown in Table 16-1. Addresses specified in the command sequence are recognized with the lower 12 ...
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Chip Erase (All Erase) This command erases the entire flash memory in approximately 30 ms. The next command sequence cannot be executed until the erase operation is completed. To check the completion of the erase operation, perform read operations ...
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Toggle Bit (D6) 16.3 Toggle Bit (D6) After the byte program, chip erase, and read protect command sequence is executed, any consecutive attempts to read from the same address is reversed bit 6 (D6) of the data (toggling between ...
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Access to the Flash Memory Area When the write, erase and read protections are set in the flash memory, read and fetch operations cannot be per- formed in the entire flash memory area. Therefore, to perform these operations in ...
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Access to the Flash Memory Area Example :After chip erasure, the program in the RAM area writes data 3FH to address F000H. ; #### Flash Memory Chip erase Process #### sLOOP1: ; #### Flash Memory Write Process #### sLOOP2: ...
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Flash Memory Control in the MCU mode In the MCU mode, write operations are performed by executing the control program in the RAM area. Before execution of the control program, copy the control program into the RAM area or ...
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Access to the Flash Memory Area Example :After sector erasure (E000H-EFFFH), the program in the RAM area writes data 3FH to address E000H. ; #### Flash Memory Sector Erase Process #### sLOOP1: ; #### Flash Memory Write Process #### ...
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Serial PROM Mode 17.1 Outline The TMP86FH12MG has a 2048 byte BOOTROM (Mask ROM) for programming to flash memory. The BOOTROM is available in the serial PROM mode, and controlled by TEST, BOOT and tion is performed via UART. ...
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Serial PROM Mode Setting 17.3 Serial PROM Mode Setting 17.3.1 Serial PROM Mode Control Pins To execute on-board programming, activate the serial PROM mode. Table 17-2 shows pin setting to activate the serial PROM mode. Note: The BOOT pin ...
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XIN XOUT VSS GND Figure 17-2 Serial PROM Mode Pin Setting Note 1: For connection of other pins, refer to " Table 17-3 Pin Function in the Serial PROM Mode ". 17.3.3 Example Connection for On-Board Writing Figure 17-3 shows ...
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Serial PROM Mode Setting 17.3.4 Activating the Serial PROM Mode The following is a procedure to activate the serial PROM mode. " Figure 17-4 Serial PROM Mode Timing " shows a serial PROM mode timing. 1. Supply power to ...
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Interface Specifications for UART The following shows the UART communication format used in the serial PROM mode. To perform on-board programming, the communication format of the write controller must also be set in the same manner. The default baud ...
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Interface Specifications for UART Table 17-5 Operating Frequency and Baud Rate in the Serial PROM Mode Reference Baud Rate (bps) Baud Rate Modification (Note 3) Data Ref. Fre- Rating quency (MHz) (MHz 1.91 to 2.10 4 3.82 ...
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Operation Command The eight commands shown in Table 17-6 are used in the serial PROM mode. After reset release, the TMP86FH12MG waits for the matching data (5AH). Table 17-6 Operation Command in the Serial PROM Mode Command Data Operating ...
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Operation Mode 6. Flash memory status output mode The status of the area from FFE0H to FFFFH, and the read protection condition are output as 7-byte code. The external controller reads this code to recognize the flash memory status. ...
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Flash Memory Erasing Mode (Operating command: F0H) Table 17-7 shows the flash memory erasing mode. Table 17-7 Flash Memory Erasing Mode Transfer Data from the External Transfer Byte Controller to TMP86FH12MG 1st byte Matching data (5AH) 2nd byte - ...
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Operation Mode 2. The 5th byte of the received data contains the command data in the flash memory erasing mode (F0H). 3. When the 5th byte of the received data contains the operation command data shown in Table 17-6, ...
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Flash Memory Writing Mode (Operation command: 30H) Table 17-8 shows flash memory writing mode process. Table 17-8 Flash Memory Writing Mode Process Transfer Data from External Controller Transfer Byte to TMP86FH12MG 1st byte Matching data (5Ah) 2nd byte - ...
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Operation Mode Description of the flash memory writing mode 1. The 1st byte of the received data contains the matching data. When the serial PROM mode is acti- vated, TMP86FH12MG (hereafter called device), waits to receive the matching data ...
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After transmitting the checksum, the device waits for the next operation command data. Note 1: Do not write only the ...
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Operation Mode 17.6.3 RAM Loader Mode (Operation Command: 60H) Table 17-9 shows RAM loader mode process. Table 17-9 RAM Loader Mode Process Transfer Bytes 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th ...
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Note error occurs during the reception of a password address or a password string, TMP86FH12MG stops UART commu- nication and enters the halt condition. In this case, initialize TMP86FH12MG by the PROM mode. Description of RAM loader ...
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Operation Mode 17.6.4 Flash Memory SUM Output Mode (Operation Command: 90H) Table 17-10 shows flash memory SUM output mode process. Table 17-10 Flash Memory SUM Output Process Transfer Bytes 1st byte 2nd byte 3rd byte 4th byte 5th byte ...