S9S08AW16AE0MFT Freescale Semiconductor, S9S08AW16AE0MFT Datasheet - Page 11

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S9S08AW16AE0MFT

Manufacturer Part Number
S9S08AW16AE0MFT
Description
MCU 16K FLASH AUTO MONET 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheets

Specifications of S9S08AW16AE0MFT

Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD. POR, PWM, WDT
Number Of I /o
38
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Controller Family/series
HCS08
No. Of I/o's
38
Ram Memory Size
1KB
Cpu Speed
40MHz
No. Of Timers
2
Rohs Compliant
Yes
Processor Series
S08AW
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
54
Number Of Timers
2
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08AW60E
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Height
1 mm
Length
7 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
7 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Section Number
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7.1
7.2
Freescale Semiconductor
Introduction .....................................................................................................................................81
Features ...........................................................................................................................................81
Pin Descriptions ..............................................................................................................................82
Parallel I/O Control .........................................................................................................................86
Pin Control ......................................................................................................................................87
Pin Behavior in Stop Modes ............................................................................................................88
Parallel I/O and Pin Control Registers ............................................................................................88
Introduction ...................................................................................................................................109
Programmer’s Model and CPU Registers .....................................................................................110
5.9.8
5.9.9
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.5.1
6.5.2
6.5.3
6.7.1
6.7.2
6.7.3
6.7.4
6.7.5
6.7.6
6.7.7
6.7.8
6.7.9
6.7.10
6.7.11
6.7.12
6.7.13
6.7.14
7.1.1
System Power Management Status and Control 1 Register (SPMSC1) .........................79
System Power Management Status and Control 2 Register (SPMSC2) .........................80
Port A ..............................................................................................................................82
Port B ..............................................................................................................................82
Port C ..............................................................................................................................83
Port D ..............................................................................................................................83
Port E ..............................................................................................................................84
Port F ..............................................................................................................................85
Port G ..............................................................................................................................85
Internal Pullup Enable ....................................................................................................87
Output Slew Rate Control Enable ..................................................................................87
Output Drive Strength Select ..........................................................................................87
Port A I/O Registers (PTAD and PTADD) .....................................................................88
Port A Pin Control Registers (PTAPE, PTASE, PTADS) ..............................................89
Port B I/O Registers (PTBD and PTBDD) .....................................................................91
Port B Pin Control Registers (PTBPE, PTBSE, PTBDS) ..............................................92
Port C I/O Registers (PTCD and PTCDD) .....................................................................94
Port C Pin Control Registers (PTCPE, PTCSE, PTCDS) ..............................................95
Port D I/O Registers (PTDD and PTDDD) ....................................................................97
Port D Pin Control Registers (PTDPE, PTDSE, PTDDS) .............................................98
Port E I/O Registers (PTED and PTEDD) ....................................................................100
Port E Pin Control Registers (PTEPE, PTESE, PTEDS) .............................................101
Port F I/O Registers (PTFD and PTFDD) ....................................................................103
Port F Pin Control Registers (PTFPE, PTFSE, PTFDS) ..............................................104
Port G I/O Registers (PTGD and PTGDD) ..................................................................106
Port G Pin Control Registers (PTGPE, PTGSE, PTGDS) ...........................................107
Features .........................................................................................................................109
Central Processor Unit (S08CPUV2)
Parallel Input/Output
MC9S08AW60 Data Sheet, Rev 2
Chapter 6
Chapter 7
Title
Page
11

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