S9S08AW16AE0MFT Freescale Semiconductor, S9S08AW16AE0MFT Datasheet - Page 143

• Manufacturer Part Number: S9S08AW16AE0MFT
• Description: MCU 16K FLASH AUTO MONET 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08AW16AE0MFT

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD. POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Controller Family/series: HCS08
• No. Of I/o's: 38
• Ram Memory Size: 1KB
• Cpu Speed: 40MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S08AW
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08AW60E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Height: 1 mm
• Length: 7 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8.4.4
FEI unlocked is a temporary state that is entered when FEI is entered and the count error (Δn) output from
the subtractor is greater than the maximum n
lock detector to detect the unlock condition.
The ICG will remain in this state while the count error (Δn) is greater than the maximum n
the minimum n
In this state the output clock signal ICGOUT frequency is given by f
8.4.5
FLL engaged internal locked is entered from FEI unlocked when the count error (Δn), which comes from
the subtractor, is less than n
required by the lock detector to detect the lock condition. The output clock signal ICGOUT frequency is
given by f
The update made is an average of the error measurements taken in the four previous comparisons.
8.4.6
FLL bypassed external (FBE) is entered when any of the following conditions occur:
In this state, the DCO and IRG are off and the reference clock is derived from the external reference clock,
ICGERCLK. The output clock signal ICGOUT frequency is given by f
source is used (REFS = 0), then the input frequency on the EXTAL pin can be anywhere in the range
0 MHz to 40 MHz. If a crystal or resonator is used (REFS = 1), then frequency range is either low for
RANGE = 0 or high for RANGE = 1.
8.4.7
The FLL engaged external (FEE) mode is entered when any of the following conditions occur:
In FEE mode, the reference clock is derived from the external reference clock ICGERCLK, and the FLL
loop will attempt to lock the ICGDCLK frequency to the desired value, as selected by the MFD bits. To
run in FEE mode, there must be a working 32 kHz–100 kHz or 2 MHz–10 MHz external clock source. The
maximum external clock frequency is limited to 10 MHz in FEE mode to prevent over-clocking the DCO.
The minimum multiplier for the FLL, from
operational limit of the DCO, the reference clock cannot be any faster than 10 MHz.
Freescale Semiconductor
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From SCM when CLKS = 10 and ERCS is high
When CLKS = 10, ERCS = 1 upon entering off mode, and off is then exited
From FLL engaged external mode if a loss of DCO clock occurs and the external reference remains
valid (both LOCS = 1 and ERCS = 1)
CLKS = 11 and ERCS and DCOS are both high.
The DCO stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 11.
ICGDCLK
FLL Engaged Internal Unlocked
FLL Engaged Internal Locked
FLL Bypassed, External Clock (FBE) Mode
FLL Engaged, External Clock (FEE) Mode
lock
, as required by the lock detector to detect the lock condition.
/ R. In FEI locked, the filter value is updated only once every four comparison cycles.
lock
(max) and greater than n
MC9S08AW60 Data Sheet, Rev 2
Table 8-12
unlock
or less than the minimum n
is 4. Because 4 X 10 MHz is 40MHz, which is the
lock
(min) for a given number of samples, as
Chapter 8 Internal Clock Generator (S08ICGV4)
ICGDCLK
ICGERCLK
/ R.
unlock
/ R. If an external clock
, as required by the
lock
or less than
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