S9S08AW16AE0MFT Freescale Semiconductor, S9S08AW16AE0MFT Datasheet - Page 97

• Manufacturer Part Number: S9S08AW16AE0MFT
• Description: MCU 16K FLASH AUTO MONET 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08AW16AE0MFT

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD. POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Controller Family/series: HCS08
• No. Of I/o's: 38
• Ram Memory Size: 1KB
• Cpu Speed: 40MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S08AW
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08AW60E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Height: 1 mm
• Length: 7 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

6.7.7
Port D parallel I/O function is controlled by the registers listed below.
Freescale Semiconductor
PTDDD[7:0]
PTDD[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
PTDDD7
PTDD7
Port D I/O Registers (PTDD and PTDDD)
Port D Data Register Bits — For port D pins that are inputs, reads return the logic level on the pin. For port D
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port D pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTDD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for
PTDD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn.
0
0
7
7
PTDDD6
PTDD6
0
0
6
6
Table 6-18. PTDDD Register Field Descriptions
Figure 6-25. Data Direction for Port D (PTDDD)
Table 6-17. PTDD Register Field Descriptions
Figure 6-24. Port D Data Register (PTDD)
PTDDD5
PTDD5
0
0
5
5
MC9S08AW60 Data Sheet, Rev 2
PTDDD4
PTDD4
0
0
4
4
Description
Description
PTDDD3
PTDD3
3
0
3
0
PTDDD2
PTDD2
0
0
2
2
Chapter 6 Parallel Input/Output
PTDDD1
PTDD1
0
0
1
1
PTDDD0
PTDD0
0
0
0
0
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