S9S08AW16AE0MFT Freescale Semiconductor, S9S08AW16AE0MFT Datasheet - Page 129

• Manufacturer Part Number: S9S08AW16AE0MFT
• Description: MCU 16K FLASH AUTO MONET 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08AW16AE0MFT

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD. POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Controller Family/series: HCS08
• No. Of I/o's: 38
• Ram Memory Size: 1KB
• Cpu Speed: 40MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S08AW
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08AW60E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Height: 1 mm
• Length: 7 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 8
Internal Clock Generator (S08ICGV4)
The internal clock generation (ICG) module is used to generate the system clocks for the MC9S08AW60
Series MCU. The analog supply lines V
V
and Timing
Freescale Semiconductor
SS
pins. Electrical parametric data for the ICG may be found in
ICG
Specifications.”
ICGERCLK
FFE
* ICGLCLK is the alternate BDC clock source for the MC9S08AW60 Series.
ICGLCLK*
ICGOUT
Freescale Semiconductor recommends that FLASH location $FFBE be
reserved to store a nonvolatile version of ICGTRM. This will allow
debugger and programmer vendors to perform a manual trim operation and
store the resultant ICGTRM value for users to access at a later time.
CPU
÷
CONTROL
SYSTEM
2
LOGIC
÷
2
FIXED FREQ CLOCK (XCLK)
Figure 8-1. System Clock Distribution Diagram
BUSCLK
RTI
MC9S08AW60 Data Sheet, Rev 2
DDA
BDC
and V
TPM1
NOTE
SSA
TPM2
are internally derived from the MCU’s V
ADC has min and max
frequency requirements.
See
“Analog-to-Digital Converter
(S08ADC10V1)
Appendix A, “Electrical
Characteristics and Timing
Specifications
Appendix A, “Electrical Characteristics
IIC1
Chapter 14,
ADC
and
SCI1
RAM
SCI2
FLASH has frequency
requirements for program
and erase operation.
See
Characteristics and Timing
Specifications.
Appendix A, “Electrical
FLASH
SPI1
DD
and
129