S9S12P64J0MFT Freescale Semiconductor, S9S12P64J0MFT Datasheet - Page 124
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S9S12P64J0MFT
Manufacturer Part Number
S9S12P64J0MFT
Description
MCU 64K FLASH AUTO 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of S9S12P64J0MFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Interrupt Module (S12SINTV1)
4.1.3
4.1.4
Figure 4-1
1. The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used
124
as upper byte) and 0x00 (used as lower byte).
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2–58 I bit maskable interrupt vector requests (at addresses vector base + 0x0082–0x00F2).
I bit maskable interrupts can be nested.
One X bit maskable interrupt vector request (at address vector base + 0x00F4).
One non-maskable software interrupt request (SWI) or background debug mode vector request (at
address vector base + 0x00F6).
One non-maskable unimplemented op-code trap (TRAP) vector (at address vector base + 0x00F8).
Three system reset vectors (at addresses 0xFFFA–0xFFFE).
Determines the highest priority interrupt vector requests, drives the vector to the bus on CPU
request
Wakes up the system from stop or wait mode when an appropriate interrupt request occurs.
Run mode
This is the basic mode of operation.
Wait mode
In wait mode, the clock to the INT module is disabled. The INT module is however capable of
waking-up the CPU from wait mode if an interrupt occurs. Please refer to
from Stop or Wait Mode”
Stop Mode
In stop mode, the clock to the INT module is disabled. The INT module is however capable of
waking-up the CPU from stop mode if an interrupt occurs. Please refer to
from Stop or Wait Mode”
Freeze mode (BDM active)
In freeze mode (BDM active), the interrupt vector base register is overridden internally. Please
refer to
shows a block diagram of the INT module.
Modes of Operation
Block Diagram
Section 4.3.1.1, “Interrupt Vector Base Register (IVBR)”
for details.
for details.
S12P-Family Reference Manual, Rev. 1.13
for details.
Section 4.5.3, “Wake Up
Section 4.5.3, “Wake Up
Freescale Semiconductor
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