S9S12P64J0MFT Freescale Semiconductor, S9S12P64J0MFT Datasheet - Page 75
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S9S12P64J0MFT
Manufacturer Part Number
S9S12P64J0MFT
Description
MCU 64K FLASH AUTO 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of S9S12P64J0MFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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1. Read: Anytime
1. Read: Always reads 0x00
2.3.21
2.3.22
Freescale Semiconductor
Address 0x0245
Address 0x0246
Write: Anytime
Write: Unimplemented
PPST
Field
Reset
Reset
7-0
W
W
R
R
Port T pull device select—Configure pull device polarity on input pin
This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.
1 A pull-down device is selected
0 A pull-up device is selected
PPST7
Port T Polarity Select Register (PPST)
PIM Reserved Register
0
0
0
7
7
= Unimplemented or Reserved
PPST6
0
0
0
6
6
Figure 2-19. Port T Polarity Select Register (PPST)
Table 2-19. PPST Register Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
Figure 2-20. PIM Reserved Register
PPST5
5
0
5
0
0
PPST4
0
0
0
4
4
Description
PPST3
0
0
0
3
3
PPST2
0
0
0
2
2
Port Integration Module (S12PPIMV1)
Access: User read/write
PPST1
0
0
0
1
1
Access: User read
PPST0
0
0
0
0
0
75
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(1)
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