S9S12P64J0MFT Freescale Semiconductor, S9S12P64J0MFT Datasheet - Page 84
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S9S12P64J0MFT
Manufacturer Part Number
S9S12P64J0MFT
Description
MCU 64K FLASH AUTO 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of S9S12P64J0MFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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1. Read: Anytime
Port Integration Module (S12PPIMV1)
2.3.35
84
Address 0x0253
Write: Anytime
DDRM
DDRM
DDRM
RDRM
Field
Field
Reset
5-0
2
1
0
W
R
Port M data direction—
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SPI the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port M data direction—
This bit determines whether the associated pin is an input or output.
The enabled CAN forces the I/O state to be an output. In this case the data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port M data direction—
This bit determines whether the associated pin is an input or output.
The enabled CAN forces the I/O state to be an input. In this case the data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port M reduced drive—Select reduced drive for output pin
This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
Port M Reduced Drive Register (RDRM)
0
0
7
Table 2-30. DDRM Register Field Descriptions (continued)
0
0
6
Figure 2-33. Port M Reduced Drive Register (RDRM)
Table 2-31. RDRM Register Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
RDRM5
5
0
RDRM4
0
4
Description
Description
RDRM3
0
3
RDRM2
0
2
Access: User read/write
Freescale Semiconductor
RDRM1
0
1
RDRM0
0
0
(1)
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