S9S12P64J0MFT Freescale Semiconductor, S9S12P64J0MFT Datasheet - Page 65
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S9S12P64J0MFT
Manufacturer Part Number
S9S12P64J0MFT
Description
MCU 64K FLASH AUTO 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of S9S12P64J0MFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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1. Read: Always reads 0x00
1. Read: Anytime. The data source is depending on the data direction value.
2. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated
2.3.7
2.3.8
Freescale Semiconductor
Function
Address 0x0004 to 0x0007
Address 0x0008
6-5, 3-2
Write: Unimplemented
Write: Anytime
pin values.
Altern.
Field
Reset
Reset
PE
PE
7
W
W
R
R
Port E general purpose input/output data—Data Register, ECLKX2 output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
Port E general purpose input/output data—Data Register
The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is
driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
ECLKX2
• The ECLKX2 output function takes precedence over the general purpose I/O function if enabled.
PIM Reserved Register
Port E Data Register (PORTE)
PE7
0
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
PE6
—
0
0
0
6
6
Table 2-8. PORTE Register Field Descriptions
Figure 2-6. Port E Data Register (PORTE)
S12P-Family Reference Manual, Rev. 1.13
Figure 2-5. PIM Reserved Register
PE5
—
5
0
0
5
0
ECLK
PE4
0
0
0
4
4
Description
PE3
—
0
0
0
3
3
PE2
—
0
0
0
2
2
Port Integration Module (S12PPIMV1)
Access: User read/write
—
PE1
IRQ
0
0
1
1
(2)
Access: User read
XIRQ
PE0
—
0
0
0
0
2
65
(1)
(1)
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