MC9S12P64CFT Freescale Semiconductor, MC9S12P64CFT Datasheet - Page 105
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MC9S12P64CFT
Manufacturer Part Number
MC9S12P64CFT
Description
MCU 16BIT 64K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of MC9S12P64CFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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2.4.4
Ports P and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or falling
edges can be individually configured on per-pin basis. All bits/pins in a port share the same interrupt
vector. Interrupts can be used with the pins configured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt
enable bit are both set. The pin interrupt feature is also capable to wake up the CPU when it is in STOP or
WAIT mode.
A digital filter on each pin prevents pulses
interrupt. The minimum time varies over process conditions, temperature and voltage
Table
Freescale Semiconductor
2-60).
Pin interrupts
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
1. These values include the spread of the oscillator frequency over temperature,
voltage and process.
Uncertain
Figure 2-65. Interrupt Glitch Filter on Port P and J (PPS=0)
Ignored
Pulse
Valid
S12P-Family Reference Manual, Rev. 1.13
t
Table 2-60. Pulse Detection Criteria
pign
t
pval
3 < t
(Figure
t
t
pulse
pulse
pulse
STOP
uncertain
< 4
≤ 3
≥ 4
2-66) shorter than a specified time from generating an
bus clocks
bus clocks
bus clocks
Unit
Mode
t
pign
STOP
< t
t
t
pulse
pulse
pulse
Port Integration Module (S12PPIMV1)
(1)
≤ t
< t
≥ t
pign
pval
pval
(Figure 2-65
and
105
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