MC9S12P64CFT Freescale Semiconductor, MC9S12P64CFT Datasheet - Page 177

• Manufacturer Part Number: MC9S12P64CFT
• Description: MCU 16BIT 64K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P64CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

access causes a match. Thus if configured for a byte access of a particular address, a word access covering
the same address does not lead to match.
Assuming the access direction is not qualified (RWE=0), for simplicity, the size access considerations are
shown in
Access direction can also be used to qualify a match for Comparator B in the same way as described for
Comparator C in
6.4.2.1.3
Comparator A offers address, direction (R/W), access size (word/byte) and data bus comparison.
Table 6-34
lower address is mapped to DBGADH. Access direction can also be used to qualify a match for
Comparator A in the same way as described for Comparator C in
Freescale Semiconductor
1. A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match.
SZE
0
0
0
0
0
0
1
1
1
1
1
1
The comparator address register must contain the exact address from the code.
Word and byte accesses of ADDR[n]
Word accesses of ADDR[n] only
Byte accesses of ADDR[n] only
Condition For Valid Match
SZ
X
X
X
X
X
X
0
0
0
0
1
1
Table
lists access considerations with data bus comparison. On word accesses the data byte of the
DBGADHM,
DBGADLM
Comparator A
$FFFF
$FFFF
$FFFF
$FF00
$00FF
$00FF
$00FF
$FF00
$FF00
$0000
$0000
$0000
6-33.
Table
Table 6-34. Comparator A Matches When Accessing ADDR[n]
6-32.
Byte
Word
Byte, data(ADDR[n])=DH
Word, data(ADDR[n])=DH, data(ADDR[n+1])=X
Word, data(ADDR[n])=X, data(ADDR[n+1])=DL
Byte, data(ADDR[n])=X, data(ADDR[n+1])=DL
Word, data(ADDR[n])=DH, data(ADDR[n+1])=DL
Byte, data(ADDR[n])=DH, data(ADDR[n+1])=DL
Word
Word, data(ADDR[n])=X, data(ADDR[n+1])=DL
Word, data(ADDR[n])=DH, data(ADDR[n+1])=X
Word, data(ADDR[n])=DH, data(ADDR[n+1])=DL
Byte
Byte, data(ADDR[n])=DH
Table 6-33. Comparator B Access Size Considerations
DH=DBGADH, DL=DBGADL
S12P-Family Reference Manual, Rev. 1.13
Comp B Address RWE
ADDR[n]
ADDR[n]
ADDR[n]
Access
(1)
0
0
0
SZE
0
1
1
Table
SZ8
No databus comparison
Match data( ADDR[n])
Match data( ADDR[n+1])
Possible unintended match
Match data( ADDR[n], ADDR[n+1])
Possible unintended match
No databus comparison
Match only data at ADDR[n+1]
Match only data at ADDR[n]
Match data at ADDR[n] & ADDR[n+1]
No databus comparison
Match data at ADDR[n]
X
0
1
6-32.
MOVB #$BYTE ADDR[n]
MOVW #$WORD ADDR[n]
MOVW #$WORD ADDR[n]
LDD ADDR[n]
MOVB #$BYTE ADDR[n]
LDAB ADDR[n]
S12S Debug Module (S12SDBGV2)
Comment
Examples
177