MC9S12P64CFT Freescale Semiconductor, MC9S12P64CFT Datasheet - Page 208
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MC9S12P64CFT
Manufacturer Part Number
MC9S12P64CFT
Description
MCU 16BIT 64K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of MC9S12P64CFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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S12 Clock, Reset and Power Management Unit (S12CPMU)
7.3.2.3
The POSTDIV register controls the frequency ratio between the VCOCLK and the PLLCLK.
Read: Anytime
Write: If PLLSEL=1 write anytime, else write has no effect.
7.3.2.4
This register provides S12CPMU status bits and flags.
Read: Anytime
208
1. PORF is set to 1 when a power on reset occurs. Unaffected by System Reset.
2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by System Reset. Set by power on reset.
3. ILAF is set to 1 when an illegal address reset occurs. Unaffected by System Reset. Cleared by power on reset.
0x0036
0x0037
Reset
Reset
If PLL is selected (PLLSEL=1)
If PLL is locked (LOCK=1)
If PLL is not locked (LOCK=0)
W
W
R
R
RTIF
S12CPMU Post Divider Register (CPMUPOSTDIV)
S12CPMU Flags Register (CPMUFLG)
0
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
Figure 7-6. S12CPMU Post Divider Register (CPMUPOSTDIV)
Note 1
PORF
0
0
6
6
Figure 7-7. S12CPMU Flags Register (CPMUFLG)
f PLL
f PLL
f bus
S12P-Family Reference Manual, Rev. 1.13
Note 2
LVRF
0
0
5
5
=
=
=
f PLL
------------ -
---------------------------------------- -
(
f VCO
---------------
POSTDIV
2
4
f VCO
LOCKIF
0
0
4
4
+
1
)
LOCK
0
0
3
3
POSTDIV[4:0]
Note 3
ILAF
0
2
2
Freescale Semiconductor
OSCIF
1
0
1
1
UPOSC
1
0
0
0
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