MC9S12P64CFT Freescale Semiconductor, MC9S12P64CFT Datasheet - Page 204
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MC9S12P64CFT
Manufacturer Part Number
MC9S12P64CFT
Description
MCU 16BIT 64K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of MC9S12P64CFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Addres
0x003A
0x003B
0x003C CPMUCOP
0x003D
0x003E
0x0034
0x0035
0x0036
0x0037
0x0038
0x0039 CPMUCLKS
0x003F
0x02F0
0x02F1
0x02F2
S12 Clock, Reset and Power Management Unit (S12CPMU)
7.3
This section provides a detailed description of all registers accessible in the S12CPMU.
7.3.1
The S12CPMU registers are shown in
204
s
CPMUTEST0
CPMUTEST1
RESERVED
RESERVED
CPMUFLG
CPMUPLL
CPMUINT
CPMURTI
POSTDIV
ARMCOP
REFDIV
APICTL
HTCTL
Memory Map and Registers
LVCTL
CPMU
CPMU
CPMU
CPMU
CPMU
CPMU
CPMU
SYNR
Name
Module Memory Map
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
PLLSEL
APICLK
RTDEC
WCOP
RTIE
Bit 7
RTIF
Bit 7
VCOFRQ[1:0]
REFFRQ[1:0]
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-3. CPMU Register Summary
S12P-Family Reference Manual, Rev. 1.13
RSBCK
PORF
PSTP
RTR6
Bit 6
6
0
0
0
0
0
0
0
0
0
Figure
WRTMASK
7-3.
RTR5
VSEL
LVRF
FM1
Bit 5
5
0
0
0
0
0
0
0
0
0
0
LOCKIE
LOCKIF
APIES
RTR4
FM0
Bit 4
4
0
0
0
0
0
0
0
0
APIEA
LOCK
RTR3
PRE
Bit 3
HTE
3
0
0
0
0
0
0
0
SYNDIV[5:0]
POSTDIV[4:0]
APIFE
HTDS
RTR2
LVDS
ILAF
PCE
CR2
Bit 2
2
0
0
0
0
0
REFDIV[3:0]
Freescale Semiconductor
OSCSEL
OSCIF
OSCIE
RTR1
HTIE
APIE
LVIE
CR1
Bit 1
RTI
1
0
0
0
0
OSCSEL
UPOSC
RTR0
HTIF
APIF
Bit 0
COP
CR0
Bit 0
LVIF
0
0
0
0
0
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