MCHC908MR8CFAE Freescale Semiconductor, MCHC908MR8CFAE Datasheet - Page 41

• Manufacturer Part Number: MCHC908MR8CFAE
• Description: IC MCU 8K FLASH 8MHZ PWM 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908MR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 16
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: HC08MR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
U = Unaffected
nate
$0000
$0001
$0002
$0003
$0004
Addr.
Data Direction Register
Port C Data Register
Port A Data Register
Port B Data Register
Register Name
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 10)
See page 281.
See page 284.
See page 287.
See page 282.
X = Indetermi-
(DDRA)
(PTC)
(PTA)
(PTB)
A
$FFD1
$FFD2
$FFFE
$FF7E
$FF7F
$FFFF
Reset:
Reset:
Reset:
↓
↓
Read:
Read:
Read:
Write:
Reset
Write:
Write:
Write:
Read
Bit 7
U
U
U
U
U
R
FLASH BLOCK PROTECT REGISTER (FLBPR)
VECTORS — 45 BYTES (46 including $FFFF)
DDRA6 DDRA5
= Reserved
PTA6
PTB6
Memory Map
U
6
0
Low byte of reset vector
UNIMPLEMENTED — 83 BYTES
COP Control Register (COPCTL)
Figure 2-1. Memory Map
PTA5
PTB5
U
5
0
DDRA4
Unaffected by reset
Unaffected by reset
Unaffected by reset
PTA4
PTB4
Bold
Unimplemented
U
4
0
ered
= Buff-
DDRA3
when read
PTA3
PTB3
U
3
0
DDRA2 DDRA1 DDRA0
PTA2
PTB2
U
2
0
= Unimplemented
PTA1
PTB1
PTC1
Technical Data
1
0
Memory Map
I/O Section
$FF7E
$FFD1
$FFD2
$FFFE
$FFFF
$FF7F
PTC0
PTA0
PTB0
Bit 0
↓
↓
0
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