MC9S12XET256MAL Freescale Semiconductor, MC9S12XET256MAL Datasheet - Page 137

• Manufacturer Part Number: MC9S12XET256MAL
• Description: MCU 16BIT 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XET256MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 12x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Cpu Family: HCS12X
• Device Core Size: 16b
• Frequency (max): 50MHz
• Interface Type: CAN/SCI/SPI
• Total Internal Ram Size: 16KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 25
• Operating Supply Voltage (typ): 1.8/2.8/5V
• Operating Supply Voltage (max): 1.98/2.9/5.5V
• Operating Supply Voltage (min): 1.72/2.7/3.13V
• On-chip Adc: 16-chx12-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 50MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
DDRM
DDRM
DDRM
DDRM
DDRM
Field
4
3
2
1
0
Port M data direction—
This register controls the data direction of pin 4.
The enabled CAN2, routed CAN0, or routed CAN4 forces the I/O state to be an input. Depending on the configuration
of the enabled routed SPI0 this pin will be forced to be input or output.In those cases the data direction bits will not
change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is
disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port M data direction—
This register controls the data direction of pin 3.
The enabled CAN1 or routed CAN0 forces the I/O state to be an output. Depending on the configuration of the
enabled routed SPI0 this pin will be forced to be input or output. In those cases the data direction bits will not change.
The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port M data direction—
This register controls the data direction of pin 2.
The enabled CAN1 or routed CAN0 forces the I/O state to be an input. Depending on the configuration of the enabled
routed SPI0 this pin will be forced to be input or output.In those cases the data direction bits will not change. The
DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port M data direction—
This register controls the data direction of pin 1.
The enabled CAN0 forces the I/O state to be an output. In those cases the data direction bits will not change. The
DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port M data direction—
This register controls the data direction of pin 0.
The enabled CAN0 forces the I/O state to be an input. In those cases the data direction bits will not change. The
DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTM or PTIM registers, when changing the
DDRM register.
Table 2-35. DDRM Register Field Descriptions (continued)
MC9S12XE-Family Reference Manual , Rev. 1.23
NOTE
Description
Chapter 2 Port Integration Module (S12XEPIMV1)
137