MC9S12XET256MAL Freescale Semiconductor, MC9S12XET256MAL Datasheet - Page 676

• Manufacturer Part Number: MC9S12XET256MAL
• Description: MCU 16BIT 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XET256MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 12x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Cpu Family: HCS12X
• Device Core Size: 16b
• Frequency (max): 50MHz
• Interface Type: CAN/SCI/SPI
• Total Internal Ram Size: 16KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 25
• Operating Supply Voltage (typ): 1.8/2.8/5V
• Operating Supply Voltage (max): 1.98/2.9/5.5V
• Operating Supply Voltage (min): 1.72/2.7/3.13V
• On-chip Adc: 16-chx12-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 50MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2)
17.5
17.5.1
Set the configuration registers before the PITE bit in the PITCFLMT register is set. Before PITE is set, the
configuration registers can be written in arbitrary order.
17.5.2
When the PITCE register bits, the PITINTE register bits or the PITE bit in the PITCFLMT register are
cleared, the corresponding PIT interrupt flags are cleared. In case of a pending PIT interrupt request, a
spurious interrupt can be generated. Two strategies, which avoid spurious interrupts, are recommended:
17.5.3
A flag is cleared by writing a one to the flag bit. Always use store or move instructions to write a one in
certain bit positions. Do not use the BSET instructions. Do not use any C-constructs that compile to BSET
instructions. “BSET flag_register, #mask” must not be used for flag clearing because BSET is a read-
modify-write instruction which writes back the “bit-wise or” of the flag_register and the mask into the
flag_register. BSET would clear all flag bits that were set, independent from the mask.
For example, to clear flag bit 0 use: MOVB #$01,PITTF.
17.6
To get started quickly with the PIT24B8C module this section provides a small code example how to use
the block. Please note that the example provided is only one specific case out of the possible configurations
and implementations.
Functionality: Generate an PIT interrupt on channel 0 every 500 PIT clock cycles.
; ******************** Start PIT Initialization *******************************************************
676
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indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
1. Reset the PIT interrupt flags only in an ISR. When entering the ISR, the I mask bit in the CCR is
2. After setting the I mask bit with the SEI instruction, the PIT interrupt flags can be cleared. Then
set automatically. The I mask bit must not be cleared before the PIT interrupt flags are cleared.
clear the I mask bit with the CLI instruction to re-enable interrupts.
Initialization
Application Information
Startup
Shutdown
Flag Clearing
ORG
LDS
MOVW
CLR
MOVB
CLR
MOVB
MOVW
CODESTART
RAMEND
#CH0_ISR,VEC_PIT_CH0 ; Change value of channel 0 ISR adr
PITCFLMT
#$01,PITCE
PITMUX
#$63,PITMTLD0
#$0004,PITLD0
MC9S12XE-Family Reference Manual , Rev. 1.23
; place the program into specific
; range (to be selected)
; load stack pointer to top of RAM
; disable PIT
; enable timer channel 0
; ch0 connected to micro timer 0
; micro time base 0 equals 100 clock cycles
; time base 0 eq. 5 micro time bases 0 =5*100 = 500
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