M38588GCSP#U0 Renesas Electronics America, M38588GCSP#U0 Datasheet
M38588GCSP#U0
Specifications of M38588GCSP#U0
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M38588GCSP#U0 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 3858 group is the 8-bit microcomputer based on the 740 fam- ily core technology. The 3858 group is designed for the household products and office automation equipment and includes serial interface functions, ...
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Group Fig. 2 Functional block diagram REJ03B0139-0111 Rev.1.11 Dec 18, 2008 page ...
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Group PIN DESCRIPTION Table 1 Pin description Pin Name Power source CNV CNV input SS SS Reference voltage V REF Analog power AVss source Reset input RESET X IN Clock input X Clock output ...
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Group PART NUMBERING Product name M3858 8 G Fig. 3 Part numbering REJ03B0139-0111 Rev.1.11 Dec 18, 2008 page – XXX SP Package type SP : PRDP0042BA PRSP0042GA-A/B ROM number –: Standard Omitted in ...
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Group GROUP EXPANSION Renesas Technology plans to expand the 3858 group as follows. Memory Type Support for QzROM version. Memory Size QzROM size ................................................................... 48 K bytes RAM size ....................................................................... 1.5 K bytes Memory Expansion Plan ROM size (bytes) ...
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Group FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 3858 group uses the standard 740 Family instruction set. Re- fer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on ...
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Group – ...
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Group [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch opera- tions can ...
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Group [CPU Mode Register (CPUM)] 003B The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B b 7 Fig. 7 Structure of CPU mode register REJ03B0139-0111 Rev.1.11 Dec 18, ...
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Group MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls ...
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Group ...
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Group I/O PORTS The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port ...
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Group ( ...
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Group (9) Port ...
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Group Fig. 12 Port block diagram (3) REJ03B0139-0111 Rev.1.11 Dec 18, 2008 page (17) Port P4 4 Pull-up control bit ...
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Group Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is ...
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Group ...
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Group INTERRUPTS The 3858 group's interrupts are a type of vector and occur by 16 sources among 19 sources: eight external, ten internal, and one software. Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt ...
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Group Table 6 Interrupt vector addresses and priority Vector Addresses (Note 1) Interrupt Source Priority High Reset (Note 2) 1 FFFD INT 2 FFFB 0 3 Timer Z1 FFF9 CNTR 2 INT 4 FFF7 1 INT 5 FFF5 2 ...
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Group Notes When setting the followings, the interrupt request bit may be set to “1”. •When setting external interrupt active edge Related register: Interrupt edge selection register (address 003A Timer XY mode register (address 0023 Timer Z1 mode register ...
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Group (INTEDGE : address 003A ...
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Group TIMERS 8-bit Timers The 3858 group has four 8-bit timers: timer 1, timer 2, timer X, and timer Y. The timer 1 and timer 2 use one prescaler in common, and the timer X and timer Y use ...
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Group (3) Event counter mode Mode selection This mode can be selected by setting “10” to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the ...
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Group “00” (1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024) “01” Divider Count source selection bit “10” X CIN Main clock division ratio selection bits f(X ) CIN CNTR active edge 0 switch bit P2 ...
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Group b7 Fig. 18 Structure of timer XY mode register REJ03B0139-0111 Rev.1.11 Dec 18, 2008 page ...
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Group ...
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Group Timer Z1 16-bit Timer The timer 16-bit timer. When the timer reaches “0000 an underflow occurs at the next count pulse and the correspond- ing timer latch is reloaded into the timer and the count ...
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Group (4) Pulse period measurement mode Mode selection This mode can be selected by setting “010” to the timer Z1 operat- ing mode bits (bits and setting “0” to the timer/event counter mode switch bit (b7) ...
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Group (6) Programmable waveform generating mode Mode selection This mode can be selected by setting “100” to the timer Z1 operat- ing mode bits (bits and setting “0” to the timer/event counter mode switch bit (b7) ...
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Group ...
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Group b 7 Fig. 21 Structure of timer Z1 mode register REJ03B0139-0111 Rev.1.11 Dec 18, 2008 page ...
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Group Fig. 22 Timing chart of timer/event counter mode ...
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Group ...
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Group ...
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Group Timer Z2 16-bit Timer The timer 16-bit timer. When the timer reaches “0000 an underflow occurs at the next count pulse and the correspond- ing timer latch is reloaded into the timer and the count ...
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Group (4) Pulse period measurement mode Mode selection This mode can be selected by setting “010” to the timer Z2 operat- ing mode bits (bits and setting “0” to the timer/event counter mode switch bit (b7) ...
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Group (6) Programmable waveform generating mode Mode selection This mode can be selected by setting “100” to the timer Z2 operat- ing mode bits (bits and setting “0” to the timer/event counter mode switch bit (b7) ...
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Group ...
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Group b 7 Fig. 29 Structure of timer Z2 mode register REJ03B0139-0111 Rev.1.11 Dec 18, 2008 page ...
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Group FFFF Fig. 30 Timing chart of timer/event counter mode FFFF Waveform output from CNTR pin 3 Fig. 31 Timing chart of ...
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Group 0000 FFFF Fig. 32 Timing chart of pulse ...
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Group FFFF Fig. ...
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Group SERIAL INTERFACE SERIAL I/O1 Serial I/O1 can be used as either clock synchronous or asynchro- nous (UART) serial I/O1. A dedicated timer is also provided for baud rate generation CLK1 ...
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Group (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to “0”. Eight serial data transfer formats can ...
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Group Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output Receive buffer read signal ST Serial input Notes 1: Error flag detection occurs at the same time that ...
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Group ...
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Group SERIAL I/O2 The serial I/O2 can be operated only as the clock synchronous type synchronous clock for serial transfer, either internal clock or external clock can be selected by the serial I/O2 synchronous clock selection bit ...
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Group X CIN Main clock division ratio selection bits (Note “0” RDY2 “1” output enable bit output enable bit RDY2 RDY2 Serial I/O2 synchronous clock selection bit CLK2 ...
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Group S CMP2 S CLK2 S OUT2 S IN2 Fig output operation CMP2 REJ03B0139-0111 Rev.1.11 Dec 18, 2008 page Judgement of I/O data comparison ...
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Group PWM (PWM: Pulse Width Modulation ) ...
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Group ...
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Group A/D CONVERTER [AD Conversion Register (ADL)] 0035 The A/D conversion register is a read-only register that stores the result of A/D conversion. Do not read out this register during conversion. [AD Control Register (ADCON)] 0034 ...
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Group WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software run-away). The watchdog timer consists of an 8-bit ...
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Group RESET CIRCUIT To reset the microcomputer, RESET pin must be held at an “L” level for 20 cycles or more Then the RESET pin is returned “H” level (the power source voltage ...
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Group ( ...
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Group CLOCK GENERATING CIRCUIT The 3858 group has two built-in oscillation circuits. An oscillation cir- cuit can be formed by connecting a resonator between X (X and X ). Use the circuit constants in accordance with the CIN COUT ...
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Group [MISRG (MISRG)] 0038 16 MISRG consists of three control bits (bits for middle-speed mode automatic switch and one control bit (bit 0) for oscillation stabilizing time set after STP instruction released. By setting the middle-speed ...
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Group Reset Middle-speed mode CM ( MHz) “1” MHz oscillating (32 kHz stopped) 4 Middle-speed mode CM ( ...
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Group Electrical characteristics Absolute maximum ratings Table 7 Absolute maximum ratings Symbol Parameter V Power source voltage CC Input voltage P0 – – REF Input voltage P2 ...
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Group Recommended operating conditions Table 8 Recommended operating conditions (V = 2 – °C, unless otherwise noted Symbol V Power source voltage CC V Power source voltage SS V A/D ...
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Group Electrical characteristics Table 9 Electrical characteristics ( 2 – °C, unless otherwise noted Symbol Parameter V “H” output voltage (Note ...
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Group Table 10 Electrical characteristics ( 2 – °C, unless otherwise noted Symbol Parameter I Power source current High-speed mode CC f(X IN ...
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Group A/D converter characteristics Table 11 A/D converter characteristics (V = 2 – °C, unless otherwise noted Symbol Parameter Resolution – Absolute accuracy ABS t ...
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Group Timing requirements Table 12 Timing requirements ( 4 – °C, unless otherwise noted Symbol Reset input “L” pulse width t (RESET) W ...
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Group Switching characteristics Table 14 Switching characteristics ( 4 – °C, unless otherwise noted Symbol CLK1 Serial I/O1 clock ...
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Group ...
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Group PACKAGE OUTLINE Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas Technology website. JEITA Package Code RENESAS Code P-SDIP42-13x36.72-1.78 PRDP0042BA SEATING PLANE e JEITA Package ...
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Group NOTES NOTES ON PROGRAMMING 1. Processor Status Register (1) Initializing of processor status register Flags which affect program execution must be initialized after a reset. In particular essential to initialize the T and D flags because ...
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Group NOTES ON PERIPHERAL FUNCTIONS Notes on Input and Output Ports 1. Notes in standby state *1 In standby state , do not make input levels of an I/O port “unde- fined”, especially for I/O ports of the N-channel ...
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Group Notes on Interrupts 1. Change of relevant register settings When the setting of the following registers or bits is changed, the interrupt request bit may be set to “1”. When not requiring the in- terrupt occurrence synchronized with ...
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Group 2. Notes when selecting clock asynchronous serial I/O (Serial I/O1) (1) Stop of transmission operation Clear the transmit enable bit to “0” (transmit disabled). <Reason> Since transmission is not stopped and the transmission circuit is not initialized even ...
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Group Notes on A/D Converter 1. Analog input pin Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0. Further, be sure to verify ...
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Group Handling of Source Pins In order to avoid a latch-up occurrence, connect a capacitor suit- able for high frequencies as bypass capacitor between power source pin (V pin) and GND pin ( source pin (V pin) ...
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REVISION HISTORY REVISION HISTORY Rev. Rev. Date Date Page Page – 1.00 First edition issued Jan.28, 2005 1.01 5 Table 2 added May.11, 2005 10 ROM code protect address, Notes added Fig. 8 partly revised 60 QzROM Version, Notes On ...
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Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained ...