M38588GCSP#U0 Renesas Electronics America, M38588GCSP#U0 Datasheet - Page 50

• Manufacturer Part Number: M38588GCSP#U0
• Description: IC 740/3858 MCU QZ-ROM 42DIP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38588GCSP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: QzROM
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 9x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3858 Group
Fig. 42 Block diagram of Serial I/O2
Fig. 43 Timing chart of Serial I/O2
REJ03B0139-0111
page 48 of 73
Receive enable signal S
S e r i a l I / O 2 o u t p u t S
T r a n s f e r c l o c k ( N o t e 1 )
N o t e s
S e r i a l I / O 2 i n p u t S
s e r i a l I / O 2 r e g i s t e r
P0
P0
P4
P0
W r i t e - i n s i g n a l t o
P0
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of CPU mode register.
1
0
3
3
1 : W h e n t h e i n t e r n a l c l o c k i s s e l e c t e d a s a t r a n s f e r c l o c k , t h e f ( X
2 : W h e n t h e i n t e r n a l c l o c k i s s e l e c t e d a s a t r a n s f e r c l o c k , t h e S
/S
/S
/S
2
/S
/S
b y s e t t i n g b i t s 0 t o 2 o f s e r i a l I / O 2 c o n t r o l r e g i s t e r 1 .
X
OUT2
IN2
CMP2
RDY2
CLK2
X
CIN
IN
Main clock division ratio
selection bits (Note)
/INT
Rev.1.11
Serial I/O2 port selection bit
Serial I/O2 port selection bit
O U T 2
RDY2
2
I N 2
Serial I/O2 I/O comparison
signal control bit
Serial I/O2
synchronous clock
selection bit
S
S
RDY2
RDY2
Serial I/O2 port selection bit
Dec 18, 2008
P0
“0”
“1”
P0
output enable bit
output enable bit
“1”
“0”
1
3
latch
latch
“0”
P4
“00”
“01”
“10”
“1”
3
S
P0
“1”
“0”
latch
RDY2
2
D
latch
0
Synchronous circuit
Synchronous circuit
Q
Serial I/O2 synchronous
Serial I/O2 synchronous
clock selection bit
clock selection bit
D
External clock
D
1
.
D
2
Optional transfer bits (3)
Optional transfer bits (3)
Serial I/O counter 2 (3)
Serial I/O counter 2 (3)
Serial I/O2 register (8)
Serial I/O2 register (8)
O U T 2
“1”
I N
“0”
) c l o c k d i v i s i o n ( f ( X
1/8
1/16
1/32
1/64
1/128
1/256
p i n h a s h i g h i m p e d a n c e a f t e r t r a n s f e r c o m p l e t i o n .
D
3
D
4
Internal synchronous
Internal synchronous
clock selection bits
clock selection bits
C I N
Serial I/O2 interrupt request bit set
) i n l o w - s p e e d m o d e ) c a n b e s e l e c t e d
D
5
Data bus
Data bus
D
6
Serial I/O2
Serial I/O2
interrupt request
interrupt request
D
7
( N o t e 2 )