MC908GT16CBE Freescale Semiconductor, MC908GT16CBE Datasheet - Page 4

IC MCU 16K FLASH 8MHZ SPI 42SDIP

MC908GT16CBE

Manufacturer Part Number
MC908GT16CBE
Description
IC MCU 16K FLASH 8MHZ SPI 42SDIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908GT16CBE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
36
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-DIP (0.600", 15.24mm)
Controller Family/series
HC08
No. Of I/o's
34
Ram Memory Size
512Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GT
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
30
Number Of Timers
4
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Package
42SPDIP
Family Name
HC08
Maximum Speed
8 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Revision History
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History (Sheet 1 of 2)
4
September,
March,
June,
2002
2002
2002
2004
Date
May,
(Continued
Revision
on next
Level
page)
N/A
1.0
2.0
3.0
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Original release
7.2 Features — Corrected third bulleted item to reflect ±4 percent variability
Figure 15-1. Forced Monitor Mode (Low) — Reworked for clarity
Figure 15-2. Forced Monitor Mode (High) — Reworked for clarity
Figure 15-3. Standard Monitor Mode — Reworked for clarity
Table 15-1. Monitor Mode Signal Requirements and Options — Reworked for
clarity
Figure 12-4. Port A I/O Circuit — Reworked to correct pullup resistor
Figure 12-11. Port C I/O Circuit — Reworked to correct pullup resistor
Figure 12-15. Port D I/O Circuit — Reworked to correct pullup resistor
Figure 2-2. Control, Status, and Data Registers — Corrected ESCI arbiter data
register (SCIADAT) to reflect read-only status
Figure 14-19. ESCI Arbiter Control Register (SCIACTL) — Corrected address
location designator from $0018 to $000A
Figure 14-20. ESCI Arbiter Data Register (SCIADAT) — Corrected address
location designator from $0019 to $000B
Reformatted to meet current publications standards
1.5.6 ADC Reference Pins (V
2.6.3 Flash Page Erase Operation — Updated procedure
2.6.4 Flash Mass Erase Operation — Updated procedure
2.6.5 Flash Program/Read Operation — Updated procedure
2.6.6 Flash Block Protection — Description updated for clarity
3.3.5 Conversion — Updated for clarity
3.6.3 ADC Voltage Reference High Pin (V
3.6.4 ADC Voltage Reference Low Pin (V
3.7.1 ADC Status and Control Register — Updated description of the COCO bit
Chapter 4 Configuration Register (CONFIG) — Updated COP tmeout selections
Chapter 4 Configuration Register (CONFIG) — Updted SSREC bit usage
Chapter 5 Computer Operating Properly (COP) Module — Updated timeout
selections
Figure 5-1. COP Block Diagram — Updated illustration for clarity
Table 6-1. Instruction Set Summary — Updated definitions for STOP and WAIT
Figure 7-9. Code Example for Switching Clock Sources — Replaced example
code
Figure 7-10. Code Example for Enabling the Clock Monitor — Replaced example
code
Figure 14-18. ESCI Prescaler Register (SCPSC) — Corrected address location
REFH
Description
and V
REFL
REFL
REFH
) — Corrected connections
) — Corrected connections
) — Corrected connections
Freescale Semiconductor
Throughout
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57, 59
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N/A
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