MC908GT16CBE Freescale Semiconductor, MC908GT16CBE Datasheet - Page 62

IC MCU 16K FLASH 8MHZ SPI 42SDIP

MC908GT16CBE

Manufacturer Part Number
MC908GT16CBE
Description
IC MCU 16K FLASH 8MHZ SPI 42SDIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908GT16CBE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
36
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-DIP (0.600", 15.24mm)
Controller Family/series
HC08
No. Of I/o's
34
Ram Memory Size
512Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GT
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
30
Number Of Timers
4
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Package
42SPDIP
Family Name
HC08
Maximum Speed
8 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Computer Operating Properly (COP) Module
The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler counter. If not cleared by
software, the COP counter overflows and generates an asynchronous reset after 262,128 or 8176
COPCLK cycles, depending on the state of the COP rate select bit, COPRS, in the configuration register.
With a 8176 COPCLK cycle overflow option, a 32.768-kHz crystal gives a COP timeout period of 250 ms.
Writing any value to location $FFFF before an overflow occurs prevents a COP reset by clearing the COP
counter and stages 12 through 5 of the prescaler.
A COP reset pulls the RST pin low for 32 COPCLK cycles and sets the COP bit in the reset status register
(RSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ1 is held at V
V
5.3 I/O Signals
The following paragraphs describe the signals shown in
5.3.1 COPCLK
COPCLK is a clock generated by the clock selection circuit in the internal clock generator (ICG). See
Clock Selection Circuit
5.3.2 STOP Instruction
The STOP instruction clears the COP prescaler.
5.3.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see
counter and clears bits 12 through 5 of the prescaler. Reading the COP control register returns the low
byte of the reset vector.
5.3.4 Power-On Reset
The power-on reset (POR) circuit clears the COP prescaler 4096 CGMXCLK cycles after power-up.
5.3.5 Internal Reset
An internal reset clears the COP prescaler and the COP counter.
62
TST
on the RST pin disables the COP.
Service the COP immediately after reset and before entering or after exiting
stop mode to guarantee the maximum time before the first COP counter
overflow.
Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from
generating a reset even while the main program is not working properly.
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
for more details.
NOTE
NOTE
Figure
5.4 COP Control
5-1.
TST
Register) clears the COP
. During the break state,
Freescale Semiconductor
7.3.5

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