DF36034GHJ Renesas Electronics America, DF36034GHJ Datasheet - Page 112
![MCU 3/5V 32K J-TEMP POR&LVD 64-Q](/photos/28/61/286103/64-bqfp__prqp0064gb-a_sml.jpg)
DF36034GHJ
Manufacturer Part Number
DF36034GHJ
Description
MCU 3/5V 32K J-TEMP POR&LVD 64-Q
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.DF36057GFZV.pdf
(594 pages)
Specifications of DF36034GHJ
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F36034GHJ
HD64F36034GHJ
HD64F36034GHJ
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Section 6 Power-Down Modes
6.1
The registers related to power-down modes are listed below.
6.1.1
SYSCR1 controls the power-down modes, as well as SYSCR2.
Rev. 4.00 Mar. 15, 2006 Page 78 of 556
REJ09B0026-0400
Bit
7
6
5
4
3 to 0
System control register 1 (SYSCR1)
System control register 2 (SYSCR2)
Module standby control register 1 (MSTCR1)
Module standby control register 2 (MSTCR2)
Bit Name
SSBY
STS2
STS1
STS0
Register Descriptions
System Control Register 1 (SYSCR1)
Initial
Value
0
0
0
0
All 0
R/W
R/W
R/W
R/W
R/W
Description
Software Standby
This bit selects the mode to transit after the execution of
the SLEEP instruction.
0: Enters sleep mode or subsleep mode.
1: Enters standby mode.
For details, see table 6.2.
Standby Timer Select 2 to 0
These bits designate the time the CPU and peripheral
modules wait for stable clock operation after exiting from
standby mode, subactive mode, or subsleep mode to
active mode or sleep mode due to an interrupt. The
designation should be made according to the clock
frequency so that the waiting time is at least 6.5 ms. The
relationship between the specified value and the number
of wait states is shown in table 6.1. When an external
clock is to be used, the minimum value (STS2 = STS1 =
STS0 =1) is recommended.
Reserved
These bits are always read as 0.
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