DF36034GHJ Renesas Electronics America, DF36034GHJ Datasheet - Page 419
![MCU 3/5V 32K J-TEMP POR&LVD 64-Q](/photos/28/61/286103/64-bqfp__prqp0064gb-a_sml.jpg)
DF36034GHJ
Manufacturer Part Number
DF36034GHJ
Description
MCU 3/5V 32K J-TEMP POR&LVD 64-Q
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.DF36057GFZV.pdf
(594 pages)
Specifications of DF36034GHJ
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F36034GHJ
HD64F36034GHJ
HD64F36034GHJ
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Table 17.1 Example of Subclock Error
Condition: System clock = 10 MHz, on-chip oscillator = 400 kHz, and subclock = 12 kHz
Count Value n
Division ratio k
Rounding error of
division ratio
Rounding error of
division ratio
error
Subclock error
In addition to the above rounding error, the subtimer may have a count error caused by time
lag between the system clock and the on-chip oscillator. The example is shown below.
After deciding the division ratio according to formulas (1) to (3), the division ratio is
configured in ROPCR. After ROPCR divides clocks of the on-chip oscillator, clocks for the
subtimer counter, input clocks to the system, and input clocks to the watchdog timer are
generated.
count
49
34
Min.
2.0
Write calculated division ratio in ROPCR
Figure 17.3 SBTPS Setting Flowchart
Configuration of division ratio completed
Start configuration of division ratio
Clear PCEF flag in SBTCTL to 0
Set OSCEB bit in SBTCTL to 1
PCEF flag in SBTCTL = 1?
Calculate division ratio
Yes
Expected Value
50
33
1.0
No
Rev. 4.00 Mar. 15, 2006 Page 385 of 556
Section 17 Subsystem Timer (Subtimer)
Max.
51
33
1.0
REJ09B0026-0400
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