DF36034GHJ Renesas Electronics America, DF36034GHJ Datasheet - Page 295
![MCU 3/5V 32K J-TEMP POR&LVD 64-Q](/photos/28/61/286103/64-bqfp__prqp0064gb-a_sml.jpg)
DF36034GHJ
Manufacturer Part Number
DF36034GHJ
Description
MCU 3/5V 32K J-TEMP POR&LVD 64-Q
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.DF36057GFZV.pdf
(594 pages)
Specifications of DF36034GHJ
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F36034GHJ
HD64F36034GHJ
HD64F36034GHJ
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14.3.8
BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 14.3
shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of
SMR in asynchronous mode. Table 14.4 shows the maximum bit rate for each frequency in
asynchronous mode. The values shown in both tables 14.3 and 14.4 are values in active (high-
speed) mode. Table 14.5 shows the relationship between the N setting in BRR and the n setting in
bits CKS1 and CKS0 of SMR in clocked synchronous mode. The values shown in table 14.5 are
values in active (high-speed) mode. The N setting in BRR and error for other operating
frequencies and bit rates can be obtained by the following formulas:
[Asynchronous Mode]
[Clocked Synchronous Mode]
[Legend]
B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0
n: CSK1 and CSK0 settings in SMR (0
: Operating frequency (MHz)
N =
Error (%) =
N =
Bit Rate Register (BRR)
64
8
2
2
2n–1
2n–1
(N + 1)
B
B
10
B
10
10
6
6
64
– 1
– 1
6
2
2n–1
n
N
3)
– 1
255)
Section 14 Serial Communication Interface 3 (SCI3)
100
Rev. 4.00 Mar. 15, 2006 Page 261 of 556
REJ09B0026-0400
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