MC9S12DP512CPVER Freescale Semiconductor, MC9S12DP512CPVER Datasheet - Page 55

IC MCU 16BIT 4K FLASH 112-LQFP

MC9S12DP512CPVER

Manufacturer Part Number
MC9S12DP512CPVER
Description
IC MCU 16BIT 4K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12DP512CPVER

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
PWM, WDT
Number Of I /o
91
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.25 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Package
112LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Operating Supply Voltage
2.5|5 V
Data Bus Width
16 Bit
Interface Type
CAN/I2C/SCI/SPI
On-chip Adc
2(8-chx10-bit)
Number Of Timers
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
MC9S12DP512CPVERTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12DP512CPVER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Pin Name
Funct. 1
PT[7:0]
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
2.3 Detailed Signal Descriptions
2.3.1 EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.
2.3.2 RESET — External Reset Pin
An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up
state, and an output when an internal MCU function causes a reset.
2.3.3 TEST — Test Pin
This input only pin is reserved for test.
2.3.4 VREGEN — Voltage Regulator Enable Pin
This input only pin enables or disables the on-chip voltage regulator.
NOTE:
Pin Name
Funct. 2
IOC[7:0]
MOSI0
MISO0
RXD1
RXD0
SCK0
TXD1
TXD0
SS0
The TEST pin must be tied to VSS in all applications.
Pin Name
Funct. 3
Pin Name
Funct. 4
Pin Name
Funct. 5
Supply
Power
VDDX
VDDX
PERS/
CTRL
PERT/
PPSS
PPST
Internal Pull
Resistor
Disabled Port T I/O, Timer channels
MC9S12DP512 Device Guide V01.25
Reset
State
Up
Port S I/O, SS of SPI0
Port S I/O, SCK of SPI0
Port S I/O, MOSI of SPI0
Port S I/O, MISO of SPI0
Port S I/O, TXD of SCI1
Port S I/O, RXD of SCI1
Port S I/O, TXD of SCI0
Port S I/O, RXD of SCI0
Description
55

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