MC9S12DP512CPVER Freescale Semiconductor, MC9S12DP512CPVER Datasheet - Page 73

• Manufacturer Part Number: MC9S12DP512CPVER
• Description: IC MCU 16BIT 4K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12DP512CPVER

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Package: 112LQFP
• Family Name: HCS12
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 2.5|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/I2C/SCI/SPI
• On-chip Adc: 2(8-chx10-bit)
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MC9S12DP512CPVERTR

Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and
interrupts.
5.2 Vectors
5.2.1 Vector Table
Table 5-1 lists interrupt sources and vectors in default order of priority.
Vector Address
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
$FFF8, $FFF9
$FFF6, $FFF7
$FFF4, $FFF5
$FFF2, $FFF3
$FFF0, $FFF1
$FFEE, $FFEF
$FFEC, $FFED
$FFEA, $FFEB
$FFE8, $FFE9
$FFE6, $FFE7
$FFE4, $FFE5
$FFE2, $FFE3
$FFE0, $FFE1
$FFDE, $FFDF
$FFDC, $FFDD
$FFDA, $FFDB
$FFD8, $FFD9
$FFD6, $FFD7
$FFD4, $FFD5
$FFD2, $FFD3
$FFD0, $FFD1
$FFCE, $FFCF
$FFCC, $FFCD
Enhanced Capture Timer channel 0
Enhanced Capture Timer channel 1
Enhanced Capture Timer channel 2
Enhanced Capture Timer channel 3
Enhanced Capture Timer channel 4
Enhanced Capture Timer channel 5
Enhanced Capture Timer channel 6
Enhanced Capture Timer channel 7
Enhanced Capture Timer overflow
Unimplemented instruction trap
Pulse accumulator input edge
Pulse accumulator A overflow
Clock Monitor fail reset
Interrupt Source
Real Time Interrupt
COP failure reset
Table 5-1 Interrupt Vector Locations
Port H
Reset
Port J
XIRQ
ATD0
ATD1
SCI0
SCI1
SPI0
SWI
IRQ
Mask
CCR
None
None
None
None
None
X-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
(PIEJ7, PIEJ6, PIEJ1, PIEJ0)
PLLCTL (CME, SCME)
SPICR1 (SPIE, SPTIE)
(TIE, TCIE, RIE, ILIE)
(TIE, TCIE, RIE, ILIE)
ATDCTL2 (ASCIE)
ATDCTL2 (ASCIE)
IRQCR (IRQEN)
COP rate select
PIEH (PIEH7-0)
CRGINT (RTIE)
Local Enable
PACTL (PAOVI)
TSRC2 (TOI)
PACTL (PAI)
MC9S12DP512 Device Guide V01.25
TIE (C0I)
TIE (C1I)
TIE (C2I)
TIE (C3I)
TIE (C4I)
TIE (C5I)
TIE (C6I)
TIE (C7I)
SCICR2
SCICR2
None
None
None
None
PIEJ
HPRIO Value
to Elevate
$EC
$DE
$DC
$CE
$CC
$EE
$EA
$DA
$D8
$D6
$D4
$D2
$D0
$F2
$F0
$E8
$E6
$E4
$E2
$E0
–
–
–
–
–
–
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