R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 315
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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9.10.3
The data bus width of the DRAM space can be selected from 8 and 16 bits by bits ABWH2 and
ABWL2 in ABWCR. DRAM with 16-bit words can be connected directly to 16-bit bus width
space.
D7 to D0 are valid in 8-bit DRAM space, and D15 to D0 are valid in 16-bit DRAM space.
The data endian format can be selected by bit LE2 in ENDIANCR. For details on the access size
and alignment, see section 9.5.6, Endian and Data Alignment.
9.10.4
Table 9.22 shows the pins used for the DRAM interface.
Table 9.22 I/O Pins for DRAM Interface
Pin
WE
RAS
LUCAS/
DQMLU
LLCAS/
DQMLL
OE
WAIT
A17 to A0
D15 to D0
Data Bus
I/O Pins Used for DRAM Interface
DRAM
Selected
WE
RAS
LUCAS
LLCAS
OE
WAIT
A17 to A0
D15 to D0
Name
Write enable
Row address
strobe
Lower-upper
column address
strobe
Lower-lower
column address
strobe
Output enable
Wait
Address pin
Data pin
I/O
Output
Output
Output
Output
Output
Input
Output
Input/
output
Function
Write enable signal for accessing the
DRAM interface
Row address strobe when the DRAM
space is specified as area 2
•
•
•
•
Output enable signal when the DRAM
space is accessed
Wait request signal used when an external
address space is accessed
Multiplexed address/data output pin
Data input/output pin
Lower-upper column address strobe
when the 32-bit DRAM space is
accessed
Upper column address strobe when the
16-bit DRAM space is accessed
Lower-lower column address strobe
when the 32-bit DRAM space is
accessed
Lower column address strobe when the
16-bit DRAM space is accessed
Rev. 2.00 Sep. 24, 2008 Page 281 of 1468
Section 9 Bus Controller (BSC)
REJ09B0412-0200
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