R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 586

• Manufacturer Part Number: R5F61663RN50FPV
• Description: MCU FLASH 384K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61663RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 EXDMA Controller (EXDMAC)
11.8.2
Bus Arbitration with Another Bus Master
A cycle of another bus master may (or not) be inserted among consecutive EXDMA transfer bus
cycles. The EXDMAC bus mastership can be set so that it is released and transferred to another
bus master.
Some of the consecutive EXDMA transfer bus cycles may be indivisible due to the transfer mode
specification, may be consecutive bus cycles for high-speed access due to the transfer mode
specification, or may be consecutive bus cycles because another bus master does not request the
bus mastership.
These consecutive EXDMA read and write cycles are indivisible: refresh cycle, external bus
release cycle, or external space access cycle by internal bus master (CPU, DTC, DMAC) does not
occur between a read cycle and a write cycle.
In cluster transfer mode, the transfer cycle in one cluster is indivisible.
In block transfer mode and auto-request burst mode, the EXDMA transfer bus cycles continues. In
this period, the bus priority level of the internal bus master is lower than the EXDMAC so that the
external space access is held pending (when EBCCS = 0 in the bus control register 2 (BCR2)).
When switching to another channel, or in the auto-request cycle steal mode, the EXDMA transfer
cycles and internal bus master cycles are alternatively executed. When the internal bus master is
not issuing an external space access cycle, the EXDMA transfer bus cycles are continuously
executed in the allowable range.
When the EBCCS bit in BCR2 is set to 1 to enable the arbitration function between the EXDMAC
and the internal bus master, the bus mastership is released, except for indivisible bus cycles, and
transferred between the EXDMAC and the internal bus master alternatively. For details, see
section 9, Bus Controller (BSC).
Rev. 2.00 Sep. 24, 2008 Page 552 of 1468
REJ09B0412-0200