R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 551
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(3)
Figure 11.36 shows an example of single address mode transfer activated by the EDREQ pin
falling edge.
EDREQ pin sampling is performed in each cycle starting at the next rise of Bφ after the end of the
DTE bit write cycle.
When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the
EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated
within the EXDMAC, the request is cleared, and EDREQ pin high level sampling for edge sensing
is started. If EDREQ pin high level sampling is completed by the end of the EXDMA single cycle,
acceptance resumes after the end of the single cycle, and EDREQ pin low level sampling is
performed again. This sequence of operations is repeated until the end of the transfer.
Bφ
EDREQ
Address bus
EDACK
EXDMA control
Channel
[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of Bφ, and request is held.
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] EXDMA cycle starts; EDREQ pin high level sampling is started at rise of Bφ.
[4], [7] When EDREQ pin high level has been sampled, acceptance is resumed after completion of write cycle.
(As in [1], EDREQ pin low level is sampled at rise of Bφ, and request is held.)
EDREQ Pin Falling Edge Activation Timing
Figure 11.36 Example of Single Address Mode Transfer Activated
Idle
[1]
Request
Minimum 3 cycles
release
Bus
[2]
Request clearance period
by EDREQ Pin Falling Edge
Single
[3]
EXDMA single
Transfer destination
Transfer source/
Acceptance resumed
Idle
[4]
Request
Minimum 3 cycles
Rev. 2.00 Sep. 24, 2008 Page 517 of 1468
[5]
Section 11 EXDMA Controller (EXDMAC)
release
Bus
Request clearance period
Single
[6]
EXDMA single
Transfer destination
Transfer source/
Acceptance resumed
Idle
REJ09B0412-0200
[7]
release
Bus
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