MC908AZ60AVFUE Freescale Semiconductor, MC908AZ60AVFUE Datasheet - Page 130

• Manufacturer Part Number: MC908AZ60AVFUE
• Description: IC MCU 61K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60AVFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-QFP
• Processor Series: HC08AZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.4 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE, ZK-HC08AX-A, M68EM08AS/AZ60AE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 15 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Clock Generator Module (CGM)
10.3.2.1 Circuits
The PLL consists of these circuits:
The operating range of the VCO is programmable for a wide range of frequencies and for maximum
immunity to external noise, including supply and CGMXFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, f
CGMXFC pin changes the frequency within this range. By design, f
center-of-range frequency, f
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK. CGMRCLK runs at a frequency,
f
running at a frequency f
The VCO’s output clock, CGMVCLK, running at a frequency f
programmable modulo divider. The modulo divider reduces the VCO clock by a factor, N. The divider’s
output is the VCO feedback clock, CGMVDV, running at a frequency f
Programming the PLL
The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock,
CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The
loop filter then slightly alters the dc voltage on the external capacitor connected to CGMXFC based on
the width and direction of the correction pulse. The filter can make fast or slow corrections depending on
its mode, as described in
and the reference frequency determines the speed of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final
reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final
reference frequency, f
on this comparison.
10.3.2.2 Acquisition and Tracking Modes
The PLL filter is manually or automatically configurable into one of two operating modes:
130
CGMRCLK
•
•
•
•
•
•
•
Voltage-controlled oscillator (VCO)
Modulo VCO frequency divider
Phase detector
Loop filter
Lock detector
Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the
VCO. This mode is used at PLL startup or when the PLL has suffered a severe noise hit and the
VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in
the PLL bandwidth control register. See
Tracking mode — In tracking mode, the filter makes only small corrections to the frequency of the
VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL
enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected
as the base clock source. See
tracking mode when it’s not in acquisition mode or when the ACQ bit is set.
, and is fed to the PLL through a buffer. The buffer output is the final reference clock, CGMRDV,
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
CGMRDV
for more information.
CGMRDV
10.3.2.2 Acquisition and Tracking
NOM
. The circuit determines the mode of the PLL and the lock condition based
, (4.9152 MHz) times a linear factor L or (L)f
= f
CGMRCLK
10.3.3 Base Clock Selector
.
10.5.2 PLL Bandwidth Control
Modes. The value of the external capacitor
CGMVCLK
CGMVRS
Circuit. The PLL is automatically in
CGMVRS
CGMVDV
. Modulating the voltage on the
, is fed back through a
is equal to the nominal
NOM
Register.
= f
.
CGMVCLK
Freescale Semiconductor
/N.
10.3.2.4