MC908AZ60AVFUE Freescale Semiconductor, MC908AZ60AVFUE Datasheet - Page 345

• Manufacturer Part Number: MC908AZ60AVFUE
• Description: IC MCU 61K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60AVFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-QFP
• Processor Series: HC08AZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.4 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE, ZK-HC08AX-A, M68EM08AS/AZ60AE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 15 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Idle
27.4.4 J1850 VPW Valid/Invalid Bits and Symbols
The timing tolerances for receiving data bits and symbols from the J1850 bus have been defined to allow
for variations in oscillator frequencies. In many cases the maximum time allowed to define a data bit or
symbol is equal to the minimum time allowed to define another data bit or symbol.
Since the minimum resolution of the BDLC for determining what symbol is being received is equal to a
single period of the MUX interface clock (t
time concurrences equal to one cycle of t
This one clock resolution allows the BDLC to differentiate properly between the different bits and symbols.
This is done without reducing the valid window for receiving bits and symbols from transmitters onto the
J1850 bus which have varying oscillator frequencies.
In Huntsinger’s’ variable pulse width (VPW) modulation bit encoding, the tolerances for both the passive
and active data bits received and the symbols received are defined with no gaps between definitions. For
example, the maximum length of a passive logic 0 is equal to the minimum length of a passive logic 1,
and the maximum length of an active logic 0 is equal to the minimum length of a valid SOF symbol.
Invalid Passive Bit
Freescale Semiconductor
An idle is defined as a passive period greater than 300 μs in length.
See
occurs between the active-to-passive transition beginning the current data bit (or symbol) and a, the
current bit would be invalid.
Figure 27-7
ACTIVE
PASSIVE
ACTIVE
PASSIVE
ACTIVE
PASSIVE
ACTIVE
PASSIVE
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
(1). If the passive-to-active received transition beginning the next data bit or symbol
Figure 27-7. J1850 VPW Received Passive Symbol Times
64 μs
a
a
128 μs
BDLC
BDLC
200 μs
b
b
), an apparent separation in these maximum time/minimum
occurs.
c
c
d
(1) INVALID PASSIVE BIT
(2) VALID PASSIVE LOGIC 0
(3) VALID PASSIVE LOGIC 1
(4) VALID EOD SYMBOL
BDLC MUX Interface
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