MC908AZ60AVFUE Freescale Semiconductor, MC908AZ60AVFUE Datasheet - Page 290

• Manufacturer Part Number: MC908AZ60AVFUE
• Description: IC MCU 61K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60AVFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-QFP
• Processor Series: HC08AZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.4 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE, ZK-HC08AX-A, M68EM08AS/AZ60AE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 15 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MSCAN Controller (MSCAN08)
23.13.4 MSCAN08 Bus Timing Register 1
SAMP — Sampling
TSEG22–TSEG10 — Time Segment
1. In this case PHASE_SEG1 must be at least 2 time quanta.
290
1. This setting is not valid. Please refer to
TSEG13
This bit determines the number of serial bus samples to be taken per bit time. If set, three samples per
bit are taken, the regular one (sample point) and two preceding samples, using a majority rule. For
higher bit rates, SAMP should be cleared, which means that only one sample will be taken per bit.
Time segments within the bit time fix the number of clock cycles per bit time and the location of the
sample point. Time segment 1 (TSEG1) and time segment 2 (TSEG2) are programmable as shown in
Table
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time
quanta (T
0
0
0
0
1
.
.
1 = Three samples per bit
0 = One sample per bit
23-8.
TSEG12
q
) clock cycles per bit as shown in
Address:
The CBTR1 register can only be written if the SFTRES bit in the MSCAN08
module control register is set.
0
0
0
0
1
.
.
Reset:
Read:
Write:
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
TSEG11
$0503
SAMP
Bit time=
Bit 7
0
0
0
1
1
1
.
.
Figure 23-18. Bus Timing Register 1 (CBTR1)
TSEG22
(1)
TSEG10
6
0
Table 23-8. Time Segment Values
0
1
0
1
1
Table 23-4
.
.
f
Pres value
MSCANCLK
TSEG21
5
0
2 T
3T
16 T
1 T
4 T
Segment 1
for valid settings.
q
q
q
Time
q
Cycles
Table
Cycles
q
Cycle
Cycles
NOTE
.
.
Cycles
TSEG20
• number of Time Quanta
4
0
(1)
(1)
(1)
23-8).
TSEG13
3
0
TSEG22
0
0
1
.
.
TSEG12
2
0
TSEG21
0
0
1
.
.
TSEG11
1
0
TSEG20
Freescale Semiconductor
0
1
1
.
.
TSEG10
Bit 0
0
1 T
2 T
Segment 2
8T
q
q
Time
q
Cycle
Cycles
Cycles
.
.
(1)