MC908AZ60AVFUE Freescale Semiconductor, MC908AZ60AVFUE Datasheet - Page 316

• Manufacturer Part Number: MC908AZ60AVFUE
• Description: IC MCU 61K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60AVFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-QFP
• Processor Series: HC08AZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.4 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE, ZK-HC08AX-A, M68EM08AS/AZ60AE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 15 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timer Interface Module A (TIMA)
25.6 TIMA During Break Interrupts
A break interrupt stops the TIMA counter and inhibits input captures.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state (see
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write I/O registers during the break state without affecting status bits.
Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit
before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the
break, doing the second step clears the status bit.
25.7 I/O Signals
Port D shares one of its pins with the TIMA. Port E shares two of its pins with the TIMA and port F shares
four of its pins with the TIMA. PTD6/ATD14/TACLK is an external clock input to the TIMA prescaler. The
six TIMA channel I/O pins are PTE2/TACH0, PTE3/TACH1, PTF0/TACH2, PTF1/TACH3, PTF2, and
PTF3.
25.7.1 TIMA Clock Pin (PTD6/ATD14/
TACLK)
PTD6/ATD14/TACLK is an external clock input that can be the clock source for the TIMA counter instead
of the prescaled internal bus clock. Select the PTD6/ATD14/TACLK input by writing logic 1s to the three
prescaler select bits, PS[2:0] (see
width, TCLK
The maximum TCLK frequency is the least: 4 MHz or bus frequency ÷ 2.
PTD6/ATD14/TACLK is available as a general-purpose I/O pin or ADC channel when not used as the
TIMA clock input. When the PTD6/ATD14/TACLK pin is the TIMA clock input, it is an input regardless of
the state of the DDRD6 bit in data direction register D.
25.7.2 TIMA Channel I/O Pins (PTF3–PTF0/TACH2 and PTE3/TACH1–PTE2/TACH0)
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
PTE2/TACH0, PTF0/TACH2 and PTF2 can be configured as buffered output compare or buffered PWM
pins.
316
LMIN
or TCLK
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
HMIN
, is:
25.8.1 TIMA Status and Control
9.7.3 SIM Break Flag Control
------------------------------------ -
bus frequency
1
+
t
SU
Register). The minimum TCLK pulse
Register).
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