D64F3437TFLH16V Renesas Electronics America, D64F3437TFLH16V Datasheet - Page 315
D64F3437TFLH16V
Manufacturer Part Number
D64F3437TFLH16V
Description
MCU 5V 60K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Datasheet
1.HD64F3437STF16V.pdf
(755 pages)
Specifications of D64F3437TFLH16V
Core Processor
H8/300
Core Size
8-Bit
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D64F3437TFLH16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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An I
For mask-ROM versions, products that use this option have a “W” added to the product number.
13.1
The I
interface functions. The register configuration that controls the I
Philips configuration, however.
The I
can save board and connector space. Figure 13.1 shows typical I
13.1.1
Conforms to Philips I
Start and stop conditions generated automatically
Selectable acknowledge output level when receiving
Auto-loading of acknowledge bit when transmitting
Selection of eight internal clocks (in master mode)
Selection of acknowledgement mode, or serial mode without acknowledge bit
Wait function: A wait can be inserted in acknowledgement mode by holding the SCL pin low
after a data transfer, before acknowledgement of the transfer.
Three interrupt sources
Direct bus drive (pins SCL and SDA)
In addition to pins SCL and SCA, four general port pins (PA
Pins P8
all powered by bus power supply V
selected, all output is NMOS output.
2
C bus interface is available as an option. Observe the following notes when using this option.
2
2
C bus interface conforms to and provides a subset of the Philips I
C bus interface uses only one data line (SDA) and one clock line (SCL) to transfer data, so it
Data transfer end
In slave receive mode: slave address matched, or general call address received
In master transmit mode: bus arbitration lost
Examples: HD6433437WTF, HD6433434WF
Overview
Features
6
/SCK
1
/SCL, P9
Section 13 I
2
C bus interface
7
/WAIT/SDA, and PA
CC
2
C Bus Interface [Option]
B, separate from V
4
/KEYIN
12
CC
to PA
. When the bus drive function is
2
4
2
C bus differs partly from the
C bus interface connections.
to PA
7
/KEYIN
2
7
C bus (inter-IC bus)
) can also drive the bus
15
(total of 6 pins) are
283
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