D64F3437TFLH16V Renesas Electronics America, D64F3437TFLH16V Datasheet - Page 345
D64F3437TFLH16V
Manufacturer Part Number
D64F3437TFLH16V
Description
MCU 5V 60K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Datasheet
1.HD64F3437STF16V.pdf
(755 pages)
Specifications of D64F3437TFLH16V
Core Processor
H8/300
Core Size
8-Bit
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Quantity
Price
Company:
Part Number:
D64F3437TFLH16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bus line
Stop condition issuing instruction
execution timing
Normal
operation
Erroneous
operation
Note on Issuance of Stop Condition
If the rise of SCL is weakened by external pull-up resistance R and bus load capacitance C in
master mode, or if SCL is pulled to the low level by a slave device, the timing at which SCL is
lowered by the internal bit synchronization circuit may be delayed by 1t SCL. If, in this case,
SCL is identified as being low at the bit synchronization circuit sampling timing, and a stop
condition issuing instruction is executed before the reference SCL clock next falls, as in figure
13.18, SDA will change from high to low to high while SCL remains high. As a result, a stop
condition will be issued before the end of the 9th clock.
Reference clock
SCL output
SDA output
SCL output
SDA output
SCL
SDA
IRIC
Figure 13.18 Stop Condition Erroneous Operation Timing
SCL identified as low
Bit synchronization circuit sampling timing
Erroneous
operation
9
9
V
IH
9th clock not ended
High interval secured
Normal operation
Stop condition
V
IH
Stop condition
313
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