UPD78F0513AGA-GAM-AX Renesas Electronics America, UPD78F0513AGA-GAM-AX Datasheet - Page 230
UPD78F0513AGA-GAM-AX
Manufacturer Part Number
UPD78F0513AGA-GAM-AX
Description
MCU 8BIT 48-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0513AGA-GAM-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
41
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0513AGA-GAM-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD78F0513AGA-GAM-AX
Manufacturer:
NEC
Quantity:
20 000
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<R>
78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Address: FF9FH
OSCCTL
Symbol
Cautions 1. Be sure to set AMPH to 1 if the high-speed system clock oscillation frequency
Remark f
Figure 6-3. Format of Clock Operation Mode Select Register (OSCCTL) (78K0/KB2)
EXCLK
EXCLK
AMPH
<7>
0
0
1
1
0
1
After reset: 00H
XH
2. Set AMPH before setting the main clock mode register (MCM).
3. Set AMPH before setting the peripheral functions after a reset release. The value of
4. If the STOP instruction is executed when AMPH = 1, supply of the CPU clock is
5. To change the value of EXCLK and OSCSEL, be sure to confirm that bit 7 (MSTOP) of
6. Be sure to clear bits 1 to 5 to 0.
: High-speed system clock oscillation frequency
exceeds 10 MHz.
AMPH can be changed only once after a reset release. When the high-speed system
clock (X1 oscillation) is selected as the CPU clock, supply of the CPU clock is
stopped for 4.06 to 16.12
clock (external clock input) is selected as the CPU clock, supply of the CPU clock is
stopped for the duration of 160 external clocks after AMPH is set to 1.
stopped for 4.06 to 16.12
speed oscillation clock is selected as the CPU clock, or for the duration of 160
external clocks when the high-speed system clock (external clock input) is selected
as the CPU clock. When the high-speed system clock (X1 oscillation) is selected as
the CPU clock, the oscillation stabilization time is counted after the STOP mode is
released.
the main OSC control register (MOC) is 1 (the X1 oscillator stops or the external
clock from the EXCLK pin is disabled).
1 MHz ≤ f
10 MHz < f
OSCSEL
OSCSEL
<6>
0
1
0
1
XH
XH
≤ 10 MHz
R/W
High-speed system clock
I/O port mode
X1 oscillation mode
I/O port mode
External clock input
mode
≤ 20 MHz
pin operation mode
0
5
μ
μ
s after the STOP mode is released when the internal high-
0
4
Operating frequency control
s after AMPH is set to 1. When the high-speed system
I/O port
Crystal/ceramic resonator connection
I/O port
I/O port
3
0
P121/X1 pin
CHAPTER 6 CLOCK GENERATOR
2
0
External clock input
P122/X2/EXCLK pin
1
0
AMPH
<0>
230
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