UPD78F0513AGA-GAM-AX Renesas Electronics America, UPD78F0513AGA-GAM-AX Datasheet - Page 529
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UPD78F0513AGA-GAM-AX
Manufacturer Part Number
UPD78F0513AGA-GAM-AX
Description
MCU 8BIT 48-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0513AGA-GAM-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
41
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0513AGA-GAM-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD78F0513AGA-GAM-AX
Manufacturer:
NEC
Quantity:
20 000
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78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(c) Switching MSB/LSB as start bit
(d) Communication start
Caution If CSIAE0 is set to 1 after data is written to SIOA0, communication does not start.
Figure 17-12 shows the configuration of serial I/O shift register 0 (SIOA0) and the internal bus. As shown in
the figure, MSB/LSB can be read/written in reverse form.
Switching MSB/LSB as the start bit can be specified using bit 1 (DIR0) of serial operation mode specification
register 0 (CSIMA0).
Start bit switching is realized by switching the bit order for data written to SIOA0. The SIOA0 shift order
remains unchanged.
Thus, switching between MSB-first and LSB-first must be performed before writing data to the shift register.
Serial communication is started by setting communication data to serial I/O shift register 0 (SIOA0) when the
following two conditions are satisfied.
• Serial interface CSIA0 operation control bit (CSIAE0) = 1
• Serial communication is not in progress
Upon termination of 8-bit communication, serial communication automatically stops and the interrupt request
flag (ACSIIF) is set.
MSB-first
LSB-first
SCKA0
Internal bus
SOA0
SIA0
7
6
1
0
Figure 17-12. Transfer Bit Order Switching Circuit
Shift register 0 (SIOA0)
Read/write gate
CHAPTER 17 SERIAL INTERFACE CSIA0
D
Q
SOA0 latch
Read/write gate
529
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