UPD78F0513AGA-GAM-AX Renesas Electronics America, UPD78F0513AGA-GAM-AX Datasheet - Page 659

• Manufacturer Part Number: UPD78F0513AGA-GAM-AX
• Description: MCU 8BIT 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AGA-GAM-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
20.4.3 Multiple interrupt servicing
1). When an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0). Therefore,
to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during interrupt servicing to
enable interrupt acknowledgment.
priority control. Two types of priority control are available: default priority control and programmable priority control.
Programmable priority control is used for multiple interrupt servicing.
being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority lower than that
of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt
servicing. Interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they
have a lower priority are held pending. When servicing of the current interrupt ends, the pending interrupt request is
acknowledged following execution of at least one main processing instruction execution.
shows multiple interrupt servicing examples.
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt.
Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected (IE =
Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to interrupt
In the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt currently
Table 20-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and Figure 20-22
Table 20-5. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing
Interrupt Being Serviced
Maskable interrupt
Software interrupt
Remarks 1.
Multiple Interrupt Request
3. ISP and IE are flags contained in the PSW.
4. PR is a flag contained in PR0L, PR0H, PR1L, and PR1H.
2. ×: Multiple interrupt servicing disabled
ISP = 0: An interrupt with higher priority is being serviced.
ISP = 1: No interrupt request has been acknowledged, or an interrupt with a lower priority is
IE = 0:
IE = 1:
PR = 0: Higher priority level
PR = 1: Lower priority level
: Multiple interrupt servicing enabled
ISP = 0
ISP = 1
being serviced.
Interrupt request acknowledgment is disabled.
Interrupt request acknowledgment is enabled.
During Interrupt Servicing
IE = 1
PR = 0
Maskable Interrupt Request
IE = 0
×
×
×
CHAPTER 20 INTERRUPT FUNCTIONS
IE = 1
×
PR = 1
IE = 0
×
×
×
Software
Interrupt
Request
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